Chrontel
CH7021/CH7022
CH7021/CH7022 SDTV/EDTV/HDTV Encoder
Features
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[1]
[2]
General Description
The CH7021/CH7022 is a Display Controller device which
accepts a digital graphics high speed AC coupled serial
differential RGB input signal, and encodes and transmits data
through analog SDTV ports (analog composite, s-video, VGA
or YPrPb) or an analog EDTV/HDTV port (YPrPb). The
device is able to encode the video signals and generate
synchronization signals for NTSC, PAL and SECAM SDTV
standards, as well as analog EDTV and HDTV interface
standards and graphics standards up to UXGA. The device
accepts one channel of RGB data over three pairs of serial
data ports.
The TV-Out processor will perform scaling to convert VGA
frames to all the supported TV output standards. Adaptive de-
flicker filter provides superior text display. Large numbers of
input graphics resolutions are supported up to 160 MHz pixel
rate with full vertical and horizontal overscan compensation in
all output standards. A high accuracy low jitter phase locked
loop is integrated to create outstanding video quality.
In addition to scaling modes, bypass modes are included
which perform color space conversion to all the TV standards
and generate and insert all the TV sync signals, or output
VGA style analog RGB.
Different analog video connectors are supported including
composite, s-video, YPrPb, SCART, D-connector and VGA
connector.
CGMS-A is also provided up to 1080i resolution. Content
protection support is provided for Macrovision
TM
in SDTV
and EDTV modes for CH7021 only.
The CH7021 is capable of adding Macrovision
TM
encoding to
the output signal. CH7022 is the same chip without
Macrovision
TM
encoding.
SDVO to SDTV/EDTV/HDTV conversion
supporting up to 160 MHz pixel clock
SDVO to VGA conversion supporting up to
1600x1200 resolution
[2]
EDTV/HDTV support for 480p, 576p, 720p, 1080i
and 1080p
Support for NTSC, PAL, SECAM color modulation.
Macrovision
TM
7.1.L1 copy protection support for
SDTV (CH7021 only)
Macrovision
TM
copy protection support for
progressive scan EDTV (480p, 576p) (CH7021 only)
CGMS-A support for SDTV, EDTV and HDTV
High-speed SDVO (1G~2Gbps) AC-coupled serial
differential RGB inputs
Flexible true scale rendering engine supports
overscan compensation in all SDTV/EDTV and
HDTV output resolutions
[3]
Text enhancement filter in scan conversion
Adaptive de-flicker filter with up to 7 lines of
filtering in scan conversion
Contrast/Brightness/Sharpness control for TV output.
Hue/Saturation Control for TV output.
Support for SCART connector
Support for EDTV / HDTV D-Connector
Outputs CVBS, S-Video, VGA and YPbPr
Support for VGA bypass
TV / Monitor connection detect
Programmable power management
Four 10-bit video DAC outputs
Three sets of DAC outputs supporting SDTV /
EDTV / HDTV / VGA connectors
Fully programmable through serial port
Configuration through Intel® SDVO OpCode
[1]
Complete Windows driver support
Offered in 64-pin LQFP and 64-pin QFN package
[1]
Intel Proprietary.
For the modes higher than 160 MHz pixel rate, please
contact Chrontel Application Department for detail.
[3]
Patent pending
201-0000-065
Rev. 2.5,
06/07/2011
1
CHRONTEL
Table of Contents
1.0
1.1
1.2
CH7021/CH7022
Pin-Out ____________________________________________________________________ 5
Package Diagram ___________________________________________________________________5
Pin Description _____________________________________________________________________7
2.0
2.1
2.2
2.3
2.4
2.5
2.6
Functional Description_______________________________________________________ 10
Input Interface_____________________________________________________________________10
TV Output Operation _______________________________________________________________10
VGA Bypass Operation _____________________________________________________________13
Command Interface ________________________________________________________________13
D-Connector ______________________________________________________________________14
Boundary scan Test_________________________________________________________________14
3.0
4.0
4.1
4.2
4.3
4.4
4.5
Register Control ____________________________________________________________ 17
Electrical Specifications ______________________________________________________ 18
Absolute Maximum Ratings __________________________________________________________18
Recommended Operating Conditions ___________________________________________________18
Electrical Characteristics ____________________________________________________________19
DC Specifications __________________________________________________________________20
AC Specifications __________________________________________________________________22
5.0
6.0
Package Dimensions _________________________________________________________ 24
Revision History ____________________________________________________________ 26
201-0000-065
Rev. 2.5,
06/07/2011
3
CHRONTEL
Figures and Tables
List of Figures
CH7021/CH7022
Figure 1: Functional Block Diagram .............................................................................................................................2
Figure 2: 64-Pin LQFP Package ....................................................................................................................................5
Figure 3: 64-Pin QFN Package......................................................................................................................................6
Figure 4: Control Bus Switch ......................................................................................................................................13
Figure 5: NAND Tree Connection ..............................................................................................................................14
Figure 6: 64 Pin LQFP (Exposed Pad) Package ..........................................................................................................24
Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................25
List of Tables
Table 1: Pin Description ................................................................................................................................................7
Table 2: CH7021/CH7022 supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns .....................10
Table 3: Various VGA resolutions. .............................................................................................................................11
Table 4: Supported SDTV standards ...........................................................................................................................11
Table 5: Supported EDTV/HDTV standards...............................................................................................................12
Table 6: Video DAC Configurations for CH7021/CH7022 ........................................................................................12
Table 7: Video Format Identification Using DL1, DL2 and DL3 ...............................................................................14
Table 8: Signal Order in the NAND Tree Testing .......................................................................................................15
Table 9: Signals not Tested in NAND Test besides power pins ..................................................................................15
Table 10: Revisions .....................................................................................................................................................26
4
201-0000-065
Rev. 2.5,
06/07/2011
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