Chrontel
CH7315B
CH7315B HDMI Transmitter
F
EATURES
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G
ENERAL
D
ESCRIPTION
The CH7315B HDMI transmitter is mixed-signal video
interface chip that transmits uncompressed, copy-
protected video and audio data over a secure link from
PCs to external television, HDTVs, DVD recorders and
A/V receivers using HDMI standard.
The CH7315B also complies with Intel SDVO (Serial
Digital Video Output} PC interface specification. The
CH7315B HDMI transmitter receives video data through
the SDVO bus, and it receives audio data from via an
Intel HD (High Definition) Audio bus. CH7315B
combines video and audio data, converting it into a single
HDMI compliant bit stream for transmission to external
CE (consumer electronics) devices. . The CH7315B
device contains HDCP cryptographic functions and
HDCP keys.
The CH7315B accepts SDVO serial input speeds of
1Gbps to 2Gbps and transmits video output at 25Mpps
(pixels per second) to 165Mpps – pixel rates that support
all HDTV display modes from 480I to 1080i/1080p.
The CH7315B device accepts RGB signals of 256-level
(0-255) or 220-level (16-235) over three pairs of serial
differential data ports, then performs the color space
conversion and outputs 256-level (0-255) or 220-level
(16-235) RGB, 4:2:2 YCbCr or 4:4:4 YcbCr data.
The CH7315B device also supports up to 8-channel audio
output at 192 KHz. audio data. Available audio
bandwidth depends on the pixel clock frequency, the
video format timing, and whether or not content
protection re-synchronization is needed.
Auto Power Saving mode is a new feature in the
CH7315B that saves PC laptop power by automatically
putting the chip into a low power consumption state if a
no-need-for-transmission situation is detected.
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Supports High-Definition Multimedia Interface
(HDMI) version 1.1 and 1.2
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High-speed SDVO (1G~2Gbps) AC-coupled serial
differential inputs
Supports Intel® High Definition Audio (HD Audio)
version 1.0
Supports S/PDIF sampling rate up to 192 kHz
Supports switched DVI/HDMI encoding two outputs
port A and B one at the time
Provides High-Bandwidth Digital Content Protection
(HDCP) version 1.1 over HDMI
Support HDMI repeater, a maximum depth of two
with maximum number of two leaves (non-repeating
receivers)
Supports HDMI video formats
(480i/576i/240p/480p/288p/576p/720p/1080i/1080p)
specified in EIA/CEA-861C, DVI and VGA outputs.
Supports DVI video formats
Supporting graphics resolutions up to 1600x1200
pixels and 1920x1200 (reduced blanking), refer to
Table 4 for more information
Supports VESA video formats for both the CVT
standard and the CEA-861-C standard
Support video pixel rate range from 25M to165M
pixels per second
Support fixed 24MHz clock input for audio data
synchronization
HDMI video low jitter PLL
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HDMI hot plug detection
Automatically enters power saving mode if TV
monitor is turned off or is disconnected from the
input video source
Chrontel’s advanced “Audio Listening Mode” can
automatically intercept digital audio stream from a
HD controller to a third party HD audio device
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Configuration through Intel® OpCodes
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Windows XP and Vista support (including MCE and Audio, video and auxiliary data are transmitted across the
three HDMI data channels. The video pixel clock is
64-bit variations)
transmitted on the HDMI clock channel. In order to
Offered in a 64-pin LQFP package
transmit audio and auxiliary data across the HDMI
channels, HDMI uses a packet structure and a special
error reduction coding.
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Intel® Proprietary.
The CH7315B features dual output ports with
dedicated DDC pins so that two external CE devices can
be connected simultaneously and can be selected one at a
time via software control. This eliminates the need to
manually switch connectors as consumers swap the active
receiving device from one connector to another. This
feature allows easy implementation of a second HDMI
output via the docking station of a notebook PC.
201-0000-079
Rev. 1.9,
1/7/2014
1
CHRONTEL
Table of Contents
1.0
1.1
1.2
CH7315B
Pin-Out ____________________________________________________________________ 4
Package Diagram ___________________________________________________________________4
Pin Description _____________________________________________________________________5
2.0
2.1
2.2
2.3
2.4
2.5
2.6
Functional Description________________________________________________________ 8
Video Input Interface ________________________________________________________________8
Audio ____________________________________________________________________________8
Power Saving ______________________________________________________________________9
HDCP Compatibility ________________________________________________________________9
HDMI Transmitter _________________________________________________________________10
Command Interface ________________________________________________________________12
3.0
4.0
4.1
4.2
4.3
4.4
4.5
Register Control ____________________________________________________________ 13
Electrical Specifications ______________________________________________________ 14
Absolute Maximum Ratings __________________________________________________________14
Recommended Operating Conditions ___________________________________________________14
Electrical Characteristics ____________________________________________________________15
DC Specifications __________________________________________________________________15
AC Specifications __________________________________________________________________18
5.0
6.0
Package Dimensions _________________________________________________________ 20
Revision History ____________________________________________________________ 21
201-0000-079
Rev. 1.9,
1/7/2014
3
CHRONTEL
1.2
Pin Description
CH7315B
Table 1: Pin Description
Pin #
1
2
4
In
In
In/Out
Type
Symbol
AUDRST*
BCLK
SC_PROM
Description
Audio Reset
This signal sources from HD audio link. When it is low, the device is in default
power on reset state.
Audio Bit Clock
24.00MHz clock sources from HD audio link.
Routed Clock Output to PROM
This pin functions as the clock bus of the serial port to PROM on ADD2 card.
This pin will require a pull-up resistor to the desired high state voltage. Leave
open if unused.
5
In/Out
SD_PROM
Routed Data to PROM
This pin functions as the bi-directional data pin of the serial port for PROM on
ADD2 card. This pin will require a pull-up resistor to the desired high state
voltage. Leave open if unused.
7
In/Out
SC_DDC0
Routed Serial Port Clock to Port A DDC
This pin functions as the clock bus of the serial port to DDC receiver. This pin
will require a pull-up resistor of 1.8kΩ to the desired high state voltage. Leave
open or tied high with a 10kΩ resistor if unused.
8
In/Out
SD_DDC0
Routed Serial Port Data to Port A DDC
This pin functions as the bi-directional data pin of the serial port to DDC
receiver. This pin will require a pull-up resistor of 1.8kΩ to the desired high
state voltage. Leave open or tied high with a 10kΩ resistor if unused.
9
10
In/Out
In/Out
SPC
SPD
Serial Port Clock Input / Output
This pin functions as the clock input of the serial port and operates with inputs
from 0 to 2.5V. This pin requires an external 2.2kΩ pull up resistor to 2.5V.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates
with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin
requires an external 2.2kΩ pull up resistor to 2.5V.
12
In/Out
SC_DDC1
13
In/Out
SD_DDC1
15
16
In
In
RESET*
VSWING
Routed Serial Port Clock to Port B DDC
This pin functions as the clock bus of the serial port to DDC receiver.
This pin will require a pull-up resistor of 5.6kΩ to the desired high
state voltage. This pin should be pulled low with a 10K ohm resistor
(recommended) or left open if unused.
Routed Serial Port Data to Port B DDC
This pin functions as the bi-directional data pin of the serial port to
DDC receiver. This pin will require a pull-up resistor of 5.6kΩ to the
desired high state voltage. This pin should be pulled low with a 10K
ohm resistor (recommended) or left open if unused.
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When
this pin is high, reset is controlled through the serial port register.
HDMI Swing Control
This pin sets the swing level of the HDMI outputs. A 1.2K-ohm resistor
should be connected between this pin and TGND using short and wide traces.
19, 20
24, 25
29, 30
34, 35
Out
Out
Out
Out
TLAC*, TLAC
TDAC0*, TDAC0
TDAC1*, TDAC1
TDAC2*, TDAC2
Rev. 1.9,
1/7/2014
HDMI Port A Clock Outputs
These pins provide the differential clock output for the HDMI port A
corresponding to data on the TDAC [2:0] outputs.
HDMI Port A Data Channel 0 Outputs
These pins provide the HDMI port A differential outputs for data channel 0
(blue).
HDMI Port A Data Channel 1 Outputs
These pins provide the HDMI port A differential outputs for data channel 1
(green).
HDMI Port A Data Channel 2 Outputs
These pins provide the HDMI port A differential outputs for data channel 2
201-0000-079
5
stm32/stm8
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