Chrontel
CH7304
CH7304 Single LVDS Transmitter
Features
• Single LVDS transmitter
• Supports pixel rate up to 100M pixels/sec
• Supports up to SXGA resolution (1280 x 1024)
• LVDS low jitter PLL
• LVDS 18-bit output
• 2D dither engine
• Panel protection and power down sequencing
• Programmable power management
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Variable voltage interface to graphics device
• Offered in a 64-pin LQFP package
General Description
The CH7304 is a Display Controller device, which accepts
a graphics data stream over one 12-bit wide variable
voltage (1.1V to 3.3V) port. The data stream outputs
through an LVDS transmitter to an LCD panel. A
maximum of 100M pixels per second can be output
through a single LVDS link.
The LVDS transmitter includes a programmable dither
function for support of 18-bit panels. Data is encoded into
commonly used formats, including those detailed in the
OpenLDI and the SPWG specification. Serialized data
output on four differential channels.
Data Mux / Format
XCLK,XCLK*
H,V, DE
D[11:0]
2
3
12
Clock,
Data,
Sync
Latch &
Demux
LVDS PLL
Color
Space
Conversion
LVDS
Encode /
Serialize
LVDS
Transmit
6
2
2
Dither
Engine
LDC[3:0],LDC*[3:0]
LLC,LLC*
ENAVDD, ENABKL
VREF
Serial Port Control and Misc. Functions
XTAL
2
XI/FIN,XO
SPC
SPD
Figure 1: Functional Block Diagram
201-0000-053
Rev. 1.31,
6/14/2006
CONFIG
RESET*
1
CHRONTEL
Table of Contents
1.0
1.1
1.2
2.0
2.1
2.2
2.3
3.0
3.1
3.2
3.3
3.4
4.0
4.1
4.2
4.3
4.4
4.5
4.6
5.0
6.0
CH7304
Pin Assignment__________________________________________________________________________ 3
Pin Diagram __________________________________________________________________________ 3
Pin Description ________________________________________________________________________ 4
Functional Description ____________________________________________________________________ 6
Input Data Formats _____________________________________________________________________ 6
LVDS-Out ___________________________________________________________________________ 9
Power Down _________________________________________________________________________ 12
Register Control ________________________________________________________________________ 13
Control Registers Index ________________________________________________________________ 13
Control Registers Description____________________________________________________________ 14
Control Registers Description____________________________________________________________ 15
Recommended Settings_________________________________________________________________ 25
Electrical Specifications __________________________________________________________________ 26
Absolute Maximum Ratings _____________________________________________________________ 26
Recommended Operating Conditions ______________________________________________________ 26
Electrical Characteristics _______________________________________________________________ 26
Digital Inputs / Outputs_________________________________________________________________ 27
AC Specifications _____________________________________________________________________ 27
Timing Information ___________________________________________________________________ 29
Package Dimensions_____________________________________________________________________ 31
Revision History ________________________________________________________________________ 32
1.0
2
201-0000-053
Rev. 1.31,
6/14/2006
CHRONTEL
Pin Assignment
1.1
Pin Diagram
CH7304
XCLK*
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DGND
DVDD
XCLK
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
ENABKL
ENAVDD
NC
NC
LVDD
NC
NC
LGND
NC
NC
LVDD
NC
NC
LGND
NC
NC
VDDV
RESET*
DE
VREF
H
V
DVDD
SPD
SPC
CONFIG
LPLL_VDD
LPLL_CAP
LPLL_GND
DGND
XI
XO
Chrontel
CH7304
LDC3
LDC2
LDC1
LDC3*
LDC2*
LDC1*
LDC0
LLC*
LDC0*
Figure 2: 64 Pin LQFP Package (Top View)
201-0000-053
Rev. 1.31, 6/14/2006
VSWING
LVDD
LGND
LGND
LVDD
LLC
LGND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3
CHRONTEL
1.2
Pin Description
Table 1: Pin Description
Pin #
1
2
3,4,6,7,9,10,
12,13,15,16
20, 21
17,23,26,29
18,24,27,30
32
# of Pins Type
1
Out
1
10
Out
-
Symbol
ENABLK
ENAVDD
NC
CH7304
Description
Back Light Enable
Enable Back-Light of LCD Panel. Output is driven from 0 to DVDD.
Panel Power Enable
Enable panel VDD. Output is driven from 0 to DVDD.
No Connect
2
4
4
1
Out
Out
Out
In
LLC, LLC*
LDC[3:0]
LDC[3:0]*
VSWING
33
1
Out
XO
34
1
In
XI
37
39
40
1
1
1
Analog
In/Out
In
LPLL_CAP
CONFIG
SPC
41
1
In/Out
SPD
43
1
In
V
44
1
In
H
45
1
In
VREF
46
1
In
DE
47
1
In
RESET*
LVDS Differential Clock
Positive LVDS differential data[3:0]
Negative LVDS differential data [3:0]
LVDS Voltage Swing Control
This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor
should be connected between this pin and LGND (pin 31) using short and
wide traces.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XI. However, if an external CMOS clock is attached
to XI, XO should be left open.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached
between this pin and XO. However, an external CMOS compatible clock
can drive the XI input.
LVDS PLL Capacitor
This pin allows coupling of any signal to the on-chip loop filter capacitor.
Configure / Output
This pin configures the device ID.
Serial Port Clock Input
This pin functions as the clock input of the serial port and can operate with
inputs from 1.1V ~ 3.3V. The serial port address of the CH7304 is 75h. For
more details on CH7304 serial port read/write operations, please refer to
AN61.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and can
operate with inputs from 1.1V ~ 3.3V. Outputs are driven from 0 to VDDV.
The serial port address of the CH7304 is 75h. For more details on CH7304
serial port read/write operations, please refer to AN61.
Vertical Sync Input
This pin accepts a vertical sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF signal is the threshold level.
Horizontal Sync Input
This pin accepts a horizontal sync input for use with the input data. The
amplitude will be 0 to VDDV. VREF is the threshold level for this input.
Reference Voltage Input
The VREF pin inputs a reference voltage of VDDV / 2. The signal is
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync and clock inputs.
Data Enable
This pin accepts a data enable signal which is high when active video data
is input to the device, and remains low during all other times. The levels
are 0 to VDDV. VREF is the threshold level.
Reset * Input (Internal Pull-up)
When this pin is low, the device is held in the power on reset condition.
When this pin is high, reset is controlled through the serial port.
4
201-0000-053
Rev. 1.31,
6/14/2006
CHRONTEL
Table 1: Pin Description (continued)
Pin #
50-55, 58-63
# of Pins Type
12
In
Symbol
D[11:0]
CH7304
Description
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port of a graphics
controller. The levels are 0 to VDDV. VREF is the threshold level.
External Clock Inputs
These inputs form a differential clock signal input to the device for use with
the H, V and D[11:0] data. If differential clocks are not available, the
XCLK* input should be connected to VREF. The clock polarity can be
selected by the MCP control bit
(
Register 1Ch
).
Digital Supply Voltage
(3.3V)
Digital Ground
I/O Supply Voltage
(1.1V to 3.3V)
LVDS Supply Voltage
(3.3V)
LVDS Ground
LVDS PLL Supply Voltage
(3.3V)
LVDS PLL Ground
56, 57
2
In
XCLK,
XCLK*
42, 64
35, 49
48
5,11,22,28
8,14,19,25,31
38
36
2
2
1
4
5
1
1
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
VDDV
LVDD
LGND
LPLL_VDD
LPLL_GND
201-0000-053
Rev. 1.31, 6/14/2006
5
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