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MCF52110CAF80

器件型号:MCF52110CAF80
器件类别:嵌入式处理器和控制器    微控制器和处理器   
文件大小:2MB,共57页
厂商名称:Rochester Electronics
厂商官网:https://www.rocelec.com/
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器件描述

RISC MICROCONTROLLER

参数
参数名称属性值
包装说明,
Reach Compliance Codeunknown
uPs/uCs/外围集成电路类型MICROCONTROLLER, RISC
Base Number Matches1

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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52110
Rev. 1, 3/2011
MCF52110
MCF52110 ColdFire
Microcontroller
Supports
MCF52110 and
MCF52100
The MCF52110 microcontroller family is a member of the
ColdFire
®
family of reduced instruction set computing
(RISC) microprocessors.
This document provides an overview of the 32-bit MCF52110
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
128 Kbytes of flash memory and 16 Kbytes of static random
access memory (SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with Multiply
Accumulate (MAC) Unit and hardware divider
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Two inter-integrated circuit (I2C™) bus interface modules
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC) with simultaneous sampling
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM), and pulse accumulation
• Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
• Two 16-bit periodic interrupt timers (PITs)
• Real-time clock (RTC) module with 32 kHz crystal
• Programmable software watchdog timer
• Secondary watchdog timer with independent clock
• Interrupt controller capable of handling 57 sources
• Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
LQFP–64
10 mm x 10 mm
QFN–64
9 mm x 9 mm
MAPBGA–81
10 mm x 10 mm
LQFP–100
14 mm x 14 mm
• Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Table of Contents
1
Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .21
1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .21
1.8 I
2
C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.9 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.10 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.11 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.12 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .23
1.13 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .23
1.14 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .23
1.15 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .24
1.16 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .
2.5 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .
2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . .
2.8 Clock Source Electrical Specifications . . . . . . . . . . . .
2.9 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
2.10 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 I
2
C Input/Output Timing Specifications . . . . . . . . . . . .
2.12 Analog-to-Digital Converter (ADC) Parameters. . . . . .
2.13 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . .
2.14 DMA Timers Timing Specifications . . . . . . . . . . . . . . .
2.15 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
2.16 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
2.17 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . .
3.1 64-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 64 QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 81 MAPBGA Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
30
31
31
32
33
34
34
36
37
38
38
38
41
42
43
46
50
52
54
3
2
4
MCF52110 ColdFire Microcontroller, Rev. 1
2
Freescale Semiconductor
Family Configurations
1
Family Configurations
Table 1. MCF52110 Family Configurations
Module
ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Flash/Static RAM (SRAM)
Interrupt Controller (INTC)
Fast Analog-to-Digital Converter (ADC)
Real-Time Clock (RTC)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Backup Watchdog Timer
Two-channel Periodic Interrupt Timer (PIT)
Four-Channel General Purpose Timer (GPT)
32-bit DMA Timers
QSPI
UART(s)
I
2
C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
1
Package
52100
52110
66, 80 MHz
up to 76
64/16 Kbytes
128/16 Kbytes
2
2
4
4
2
2
3
2
64 LQFP/QFN
81 MAPBGA
64 LQFP/QFN
81 MAPBGA
100 LQFP
1
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is
bonded on smaller packages.
MCF52110 ColdFire Microcontroller, Rev. 1
3
Freescale Semiconductor
Family Configurations
1.1
Block Diagram
Slave Mode Access
(CIM_IBO/EzPort)
Figure 1
shows a top-level block diagram of the device. Package options for this family are described later in this document.
AN
QSPI
SDAn
SCLn
UTXDn
PADI – Pin Muxing
URXDn
URTSn
UCTSn
PWMn
DTINn/DTOUTn
GPT
RCON_B
ALLPST
PST
DDATA
Arbiter
M2 M0
TMS
TDI
TDO
TRST
TCLK
M1
Interrupt
Controller
BDM
PORT
UART
0
JTAG
TAP
UART
1
UART
2
I
2
C
0
QSPI
Watch
Dog
JTAG_EN
DTIM
0
DTIM
1
DTIM
2
DTIM
3
RTC
I
2
C
1
4 CH
DMA
V2 ColdFire CPU
MAC
DIV
PMM
IPS Bus Gasket
AN[7:0]
CIM_IBO
ADC
Backup
Watchdog
16 Kbytes
SRAM
CFM
128 Kbytes
flash memory
(16K16)4
V
PP
CLKMOD
PORTS
CIM_IBO
RSTI
RSTO
V
STBY
TIM
Edge
Port
EXTAL
IRQ[7:1]
PLL OCO
CLKGEN
XTAL
CLKOUT
PIT0
PIT1
PWM
GPT[3:0]
Figure 1. MCF52110 Block Diagram
1.2
1.2.1
Features
Feature Overview
The MCF52110 family includes the following features:
MCF52110 ColdFire Microcontroller, Rev. 1
Freescale Semiconductor
4
与MCF52110CAF80相近的元器件有:MCF52110CAE66、MCF52110CEP66、MCF52110CAE80。描述及对比如下:
型号 MCF52110CAF80 MCF52110CAE66 MCF52110CEP66 MCF52110CAE80
描述 RISC MICROCONTROLLER RISC MICROCONTROLLER RISC MICROCONTROLLER RISC MICROCONTROLLER
Reach Compliance Code unknown unknown unknown unknown
uPs/uCs/外围集成电路类型 MICROCONTROLLER, RISC MICROCONTROLLER, RISC MICROCONTROLLER, RISC MICROCONTROLLER, RISC
Base Number Matches 1 1 1 1
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