SSF10N65
650V N-Channel MOSFET
Main Product Characteristics
V
DSS
R
DS
(on)
I
D
650V
0.9Ω (typ.)
10A
TO-220
Marking and Pin
Assignment
Schematic Diagram
Features and Benefits
Advanced MOSFET process technology
Special designed for PWM, load switching and
general purpose applications
Ultra low on-resistance with low gate charge
Fast switching and reverse body recovery
150℃ operating temperature
Lead free product
Description
It utilizes the latest processing techniques to achieve the high cell density and reduces the on-resistance with
high repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable
device for use in power switching application and a wide variety of other applications.
Absolute Max Rating
Symbol
I
D
@ TC = 25°C
I
D
@ TC = 100°C
I
DM
P
D
@TC = 25°C
V
DS
V
GS
E
AS
I
AS
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V①
Continuous Drain Current, V
GS
@ 10V①
Pulsed Drain Current②
Power Dissipation③
Linear Derating Factor
Drain-Source Voltage
Gate-to-Source Voltage
Single Pulse Avalanche Energy @ L=19.5mH
Avalanche Current @ L=19.5mH
Operating Junction and Storage Temperature Range
Max.
10
6
40
156
1.25
650
± 30
772
8.9
-55 to +150
W
W/°C
V
V
mJ
A
°C
A
Units
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Page 1 of 7
Rev.1.0
SSF10N65
650V N-Channel MOSFET
Thermal Resistance
Symbol
R
θJC
R
θJA
Characteristics
Junction-to-case③
Junction-to-ambient (t ≤ 10s)
④
Junction-to-Ambient (PCB mounted, steady-state)
④
Typ.
—
—
—
Max.
0.8
62
40
Units
℃/W
℃/W
℃/W
Electrical Characteristics
@T
A
=25℃
Symbol
V
(BR)DSS
R
DS(on)
Parameter
Drain-to-Source breakdown voltage
Static Drain-to-Source on-resistance
Min.
650
—
—
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
unless otherwise specified
Typ.
—
0.9
2.02
—
1.88
—
—
—
—
22.98
8.01
10.22
21.60
37.84
56.88
36.40
1186
132
2.68
Max.
—
1.0
—
4
—
1
50
100
-100
—
—
—
—
—
—
—
—
—
—
pF
V
GS
= 0V
V
DS
= 25V
ƒ = 1MHz
ns
nC
Units
V
Ω
Conditions
V
GS
= 0V, ID = 250μA
V
GS
=10V,I
D
= 5A
T
J
= 125℃
V
V
DS
= V
GS
, I
D
= 250μA
T
J
= 125℃
μA
V
DS
= 650V,V
GS
= 0V
T
J
= 125℃
nA
V
GS
=30V
V
GS
= -30V
I
D
= 9.5A,
V
DS
=480V,
V
GS
= 10V
V
GS
=10V, VDS=320V,
R
L
=33.8Ω,R
GEN
=25Ω
ID=9.5A
V
GS(th)
Gate threshold voltage
I
DSS
Drain-to-Source leakage current
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
Gate-to-Source forward leakage
Total gate charge
Gate-to-Source charge
Gate-to-Drain("Miller") charge
Turn-on delay time
Rise time
Turn-Off delay time
Fall time
Input capacitance
Output capacitance
Reverse transfer capacitance
Source-Drain Ratings and Characteristics
Symbol
I
S
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Min.
—
Typ.
—
Max.
10
Units
A
Conditions
MOSFET symbol
showing the
integral reverse
p-n junction diode.
I
S
=10A, V
GS
=0V
T
J
= 25°C, I
F
=9.5A,
di/dt = 100A/μs
I
SM
V
SD
t
rr
Q
rr
—
—
—
—
—
0.91
739
5313
40
1.4
—
—
A
V
ns
nC
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Page 2 of 7
Rev.1.0
SSF10N65
650V N-Channel MOSFET
Test Circuits and Waveforms
Switch Waveforms:
Notes:
①The
maximum current rating is limited by bond-wires.
②Repetitive
rating; pulse width limited by max. junction temperature.
③The
power dissipation PD is based on max. junction temperature, using junction-to-case thermal
resistance.
④The
value of
R
θJA
is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a
still air environment with TA =25°C
⑤These
curves are based on the junction-to-case thermal impedence which is measured with the
device mounted to a large heatsink, assuming a maximum junction temperature of T
J(MAX)
=150°C.
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Page 3 of 7
Rev.1.0
SSF10N65
650V N-Channel MOSFET
Typical Electrical and Thermal Characteristics
Figure 1: Typical Output Characteristics
Figure 2. Gate to source cut-off voltage
Figure 3. Drain-to-Source Breakdown Voltage Vs.
Case Temperature
Figure 4: Normalized On-Resistance Vs. Case
Temperature
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Page 4 of 7
Rev.1.0
SSF10N65
650V N-Channel MOSFET
Typical Electrical and Thermal Characteristics
Figure 5. Maximum Drain Current Vs. Case
Temperature
Figure 6.Typical Capacitance Vs. Drain-to-Source
Voltage
Figure7. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 5 of 7
Rev.1.0
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