ESMT
Mobile DDR SDRAM
M53D128168A
Operation Temperature Condition -40°C~85°C
2M x 16 Bit x 4 Banks
Mobile
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Quad bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
Special function support
-
PASR (Partial Array Self Refresh)
-
Internal TCSR (Temperature Compensated Self
Refresh)
-
DS (Driver Strength)
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
V
DD
/V
DDQ
= 1.7V ~ 1.9V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
1.8V LVCMOS-compatible inputs
60 ball BGA package
Ordering information :
Part NO.
M53D128168A -7.5BAIG
M53D128168A -10BAIG
MAX FREQ
133MHz
100MHz
VDD
1.8V
PACKAGE
8x13 mm
BGA
COMMENTS
Pb-free
Pb-free
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
DQS
Sense Amplifier
DM
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
1/46
ESMT
Pin Arrangement
60 Ball BGA (8x13mm)
TOP View
1
A
B
C
D
E
F
G
H
J
K
L
M
V
SSQ
DQ14
DQ12
DQ10
DQ8
NC
M53D128168A
Operation Temperature Condition -40°C~85°C
2
DQ15
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
CLK
NC
A11
A8
A6
A4
3
V
SS
DQ13
DQ11
DQ9
UDQS
7
V
DD
DQ2
DQ4
DQ6
LDQS
8
DQ0
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
CAS
CS
BA0
A10/AP
9
V
DDQ
DQ1
DQ3
DQ5
DQ7
NC
UDM
CLK
CKE
A9
A7
A5
V
SS
LDM
WE
RAS
BA1
A0
A2
V
DD
A1
A3
Pin Description
Pin Name
Function
Address inputs
- Row address A0~A11
- Column address A0~A8
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
Pin Name
Function
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
No connection
A0~A11,
BA0,BA1
LDM, UDM
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
NC
V
SS
V
DD
LDQS, UDQS
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
2/46
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
V
DDQ
T
STG
P
D
I
OS
M53D128168A
Operation Temperature Condition -40°C~85°C
Value
-0.5 ~ 2.7
-0.5 ~ 2.7
-0.5 ~ 2.7
-55 ~ +150
1.0
50
Unit
V
V
V
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= -40 to 85 °C )
Parameter
Supply voltage
I/O Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Notes:
1. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
.
Symbol
V
DD
V
DDQ
V
IH
(DC)
V
IL
(DC)
V
OH
(DC)
V
OL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
Min
1.7
1.7
0.7 x V
DDQ
-0.3
0.9 x V
DDQ
-
-0.3
0.4 x V
DDQ
-2
-5
Max
1.9
1.9
V
DDQ
+ 0.3
0.3 x V
DDQ
-
0.1 x V
DDQ
V
DDQ
+ 0.3
V
DDQ
+ 0.3
2
5
Unit
V
V
V
V
V
V
V
V
1
I
OH
= -0.1mA
I
OL
= 0.1mA
Note
μ
A
μ
A
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
3/46
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T
A
= -40 to 85 °C
Parameter
Operating Current
(One Bank Active)
Symbol
I
CC0
I
CC2P
Precharge Standby
Current in power-down
mode
Test Condition
M53D128168A
Operation Temperature Condition -40°C~85°C
Version
-7.5
60
-10
50
Unit
mA
mA
t
RC
= t
RC
(min), t
CK
= t
CK
(min), CKE = High,
/CS = High between valid commands, address
inputs are switching, data input signals are stable
All banks idle,
CKE = Low, /CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
All banks idle,
CKE = Low, /CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
All banks idle,
CKE = Low, /CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
All banks idle,
CKE = Low, CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
One bank active,
CKE = Low, CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
One bank active,
CKE = Low, CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
One bank active,
CKE = Low, CS = High, t
CK
= t
CK
(min), address &
control inputs are switching, data input signals are
stable
One bank active,
CKE = Low, CS = High, t
CK
= Low,
/t
CK
(min) =High, address & control inputs are
switching, data input signals are stable
One bank active,
BL=4, t
CK
= t
CK
(min), continuous read bursts,
I
OUT
= 0 mA, address inputs are switching, 50%
data changing each burst
One bank active,
BL=4, t
CK
= t
CK
(min), continuous write bursts,
I
OUT
= 0 mA, address inputs are switching, 50%
data changing each burst
Burst refresh,
t
RC
= t
RC
(min), t
CK
= t
CK
(min), CKE = High,
address inputs are switching, data input signals
are stable
0.5
I
CC2PS
0.5
mA
Precharge Standby
Current in non
power-down mode
I
CC2N
28
22
mA
I
CC2NS
28
22
mA
I
CC3P
Active Standby Current
in power-down mode
I
CC3PS
5
mA
2
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3N
45
35
mA
I
CC3NS
25
20
mA
Operating Current
(Burst Mode)
I
CC4R
90
75
mA
I
CC4W
90
75
mA
Refresh Current
I
CC5
75
60
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
4/46
ESMT
Self Refresh Current
I
CC6
CKE = Low, CS = High,
t
ck
= t
ck
(min), address &
control & data inputs are
stable
4 Banks
2 Bank
1 Bank
Deep Power Down
Current
I
CC7
address & control & data inputs are stable
M53D128168A
Operation Temperature Condition -40°C~85°C
TCSR range
15
340
290
240
45
360
310
260
10
70
380
320
280
85
400
350
300
°C
uA
uA
Note: 1. It has +/- 5
°C
tolerance.
2. I
CC
specifications are tested after the device is properly intialized.
3. Definitions for I
CC
: LOW is defined as V
IN
≤
0.1 * V
DDQ
;
HIGH is defined as V
IN
≥
0.9 * V
DDQ
;
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once
per two clock cycles ;
- data bus inputs: DQ changing between HIGH and LOW once per clock
cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
Min
0.8 x V
DDQ
-0.3
0.6 x V
DDQ
0.4 x V
DDQ
Max
V
DDQ
+0.3
0.2 x V
DDQ
V
DDQ
+0.3
0.6 x V
DDQ
Unit
V
V
V
V
1
2
Note
Note1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 1.8V, V
DDQ
=1.8V, T
A
= 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
1.5
1.5
2.0
2.0
Max
3.0
3.5
4.5
4.5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2008
Revision : 1.0
5/46
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
