ESMT
Mobile SDRAM
M52S64322A
512K x 32 Bit x 4 Banks
Mobile Synchronous DRAM
FEATURES
2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
EMRS cycle with address
All inputs are sampled at the positive going edge of the
system clock
Special function support
-
PASR (Partial Array Self Refresh)
-
TCSR (Temperature Compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
PRODUCT NO.
M52S64322A-7.5BG
M52S64322A-10BG
MAX
FREQ.
133MHz
100MHz
PACKAGE
90 Ball FBGA
90 Ball FBGA
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
The M52S64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by
32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
90 Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
WE
A1
NC
RAS
DQM0
VDDQ DQ8
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
1/47
ESMT
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
M52S64322A
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DQM 0~3
Column Decoder
Data Control Circuit
DQ
PIN FUNCTION DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A10
BA0 , BA1
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0~3.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS
Row Address Strobe
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS
Column Address Strobe
CAS low.
Enables column access.
Enables write operation and row precharge.
WE
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
DQM0~3
DQ0 ~ DQ31
VDD / VSS
VDDQ / VSSQ
NC
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
2/47
ESMT
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note:
SYMBOL
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
VALUE
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1
50
M52S64322A
UNIT
V
V
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
°
C )
PARAMETER
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
SYMBOL
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
MIN
2.3
0.8xV
DDQ
-0.3
V
DDQ
-0.2
-
-10
-10
TYP
2.5
-
0
-
-
-
-
MAX
2.7
V
DDQ
+0.3
0.3
-
0.2
10
10
UNIT
V
V
V
V
V
1
2
I
OH
= -0.1mA
I
OL
= 0.1mA
3
4
NOTE
μ
A
μ
A
1. V
IH
(max) = 3.0V AC for pulse width
≤
3ns acceptable.
2. V
IL
(min) = -1.0V AC for pulse width
≤
3ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DDQ
, all other pins are not under test = 0V.
4. D
out
is disabled, 0V
≤
V
OUT
≤
V
DDQ
.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 25
°
C , f = 1MHz)
PARAMETER
Input capacitance (A0 ~ A10, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
& DQM)
Data input/output capacitance (DQ0 ~ DQ31)
C
OUT
-
6
pF
SYMBOL
C
IN1
C
IN2
MIN
-
-
MAX
4
4
UNIT
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
3/47
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T
A
= 0 to 70
°
C
M52S64322A
Version
Parameter
Symbol
Test Condition
-7.5
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
I
CC1
I
CC2P
I
CC2PS
I
CC2N
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=10ns
Input signals are changed one time during 20ns
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3P
I
CC3PS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA, Page Burst
All Band Activated, t
CCD
= t
CCD
(min)
t
RFC
≥
t
RFC
(min)
TCSR range
4 Banks
Self Refresh Current
I
CC6
CKE
≤
0.2V
2 Bank
1 Bank
1/2 Bank
Deep Power Down
Current
I
CC7
CKE
≤
0.2V
110
115
70
420
350
uA
300
300
50
uA
40
80
110
mA
mA
mA
1
2
7
5
mA
5
50
mA
mA
70
1
0.5
10
-10
60
Unit Note
mA
mA
mA
mA
1
I
CC3N
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
I
CC4
I
CC5
°C
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
4/47
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V, T
A
= 0 °C ~ 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
M52S64322A
Unit
V
V
ns
V
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
@ Auto refresh
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Mode Register command to Active or Refresh
Command
Refresh period(4K cycle)
Number of valid output
data
Symbol
-7.5
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
Row cycle time
t
RC
(min)
t
RFC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
t
MRD
(min)
t
REF
(max)
CAS latency=3
CAS latency=2
75
75
1
2
1
1
2
64
2
1
15
20
20
45
100
100
100
Version
-10
20
30
30
50
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
CLK
ms
ea
1
1
1
1
-
1
1,5
2
2
2
3
-
6
4
Unit
Note
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks
5. A new command may be given t
RFC
after self refresh exit.
6. A maximum of eight consecutive AUTO REFRESH commands (with t
RFCmin
) can be posted to any given SDRAM, and
the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is
8x15.6μs.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2009
Revision: 1.3
5/47
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