ESMT
PSRAM
Features
‧Advanced
low-power architecture
• High speed: 55 ns, 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 2 mA @ f = 1 MHz
• Typical active current: 11 mA @ f = f
MAX
• Low standby power
• Automatic power-down when deselected
M24L816512SA
8-Mbit (512K x 16)
Pseudo Static RAM
Byte Low Enable are disabled (
BHE
,
BLE
HIGH), or during
a write operation ( CE LOW and
WE
LOW).
Writing to the device is accomplished by taking Chip
Enable( CE LOW) and Write Enable (
WE
) input LOW. If
Byte Low Enable (
BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is written into the location specified on the
address pins(A
0
through A
18
). If Byte High Enable (
BHE
) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written
into the location specified on the address pins (A
0
through
A
18
).
Reading from the device is accomplished by taking Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable (
WE
) HIGH. If Byte Low Enable
(
BLE
) is LOW, then data from the memory location specified
by the address pins will appear on I/O
0
to I/O
7
. If Byte High
Enable(
BHE
) is LOW, then data from memory will appear on
I/O
8
toI/O
15
. Refer to the truth table for a complete description
of read and write modes.
Functional Description
The M24L816512SA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both
BHE
and
BLE
are HIGH).
The input/output pins (I/O0through I/O
15
) are placed in a
high-impedance state when : deselected ( CE
HIGH),
outputs are disabled (
OE
HIGH), both Byte High Enable
and
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2009
Revision
:
1.5
1/14
ESMT
Pin Configuration[2, 3, 4]
48-ball VFBGA
Top View
M24L816512SA
44-Pin TSOPII(Note*)
Top View
(Default)
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
V
SS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BL E
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
V
SS
V
CC
I/ O1 1
I/ O1 0
I/ O9
I/ O8
A1 8
A8
A9
A1 0
A11
A1 7
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
CC
V
SS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(TypeA)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
V
SS
V
CC
I/O 11
I/O 10
I/O 9
I/O 8
A8
A9
A1 0
A11
A1 2
A1 3
Note* :
The default pin arrangement of TSOPII package of the device is as ”Default” figure.
User also can control pin 18~28 to turn into pin arrangement of “Type A” with software.
(The difference in pin arrangement between ”Default” and “Type A” is pin 18~28)
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2009
Revision
:
1.5
2/14
ESMT
Product Portfolio Product
M24L816512SA
Power Dissipation
Product
Min.
M24L816512SA
2.7
V
CC
Range (V)
Speed(ns)
Max.
3.6
55
70
Operating I
CC
(mA)
f = 1MHz
Typ.[5]
2
Max.
5
f = f
MAX
Typ.[5]
11
Max.
22
17
Standby, I
SB2
(µA)
Typ. [5]
55
100
110(for Vcc > 3.3V)
Max.
Typ.
3.0
Notes:
2.DNU pins are to be left floating or tied to VSS.
3.Ball G2, H6 are the address expansion pins for the 16-Mbit and 32-Mbit densities respectively.
4.NC “no connect”—not connected internally to the die.
5.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC (typ)
and T
A
= 25°C.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2009
Revision
:
1.5
3/14
ESMT
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to Ground Potential ................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V
DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ............................20 mA
M24L816512SA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Extended
Industrial
Ambient
Temperature (T
A
)
−25°C
to +85°C
−40°C
to +85°C
V
CC
2.7V to 3.6V
2.7V to 3.6V
DC Electrical Characteristics (Over the Operating Range) [5, 6, 7, 8]
-55
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current
—CMOS Inputs
Automatic CE
Power-Down
Current
—CMOS Inputs
Test Conditions
Min.
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
0.8*
V
CC
-0.4
-1
-1
11
2
2.7
V
CC
-
0.4
Typ
.[5]
3.0
Max.
3.6
Min.
2.7
V
CC
-
0.4
0.8*
V
CC
-0.4
-1
-1
11
2
-70
Typ.
[5]
3.0
Unit
Max.
3.6
V
V
0.4
V
CC
+0
.4V
0.4
+1
+1
17
5
mA
V
V
V
µA
µA
0.4
V
CC
+
0.4V
0.4
+1
+1
22
5
f=0
GND
≤
V
IN
< V
CC
GND
≤
V
OUT
≤
V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 3.6V
I
OUT
= 0mA
CMOS level
I
SB1
CE
≥
V
CC
−
0.2V, V
IN
≥
V
CC
−
0.2V, V
IN
≤
0.2V, f = f
MAX
(Address and Data
Only), f = 0
BLE
)
( OE ,
WE
,
BHE
and
100
400
100
400
µA
I
SB2
CE
≥
V
CC
−0.2V,
V
IN
≥
V
CC
−
0.2V or
V
IN
≤
0.2V,
f=0
V
CC
= 3.3V
V
CC
= 3.6V
55
100
110
55
100
110
µA
Capacitance[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance[9]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance(Junction to Ambient)
Thermal Resistance (Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
BGA
55
17
Unit
°C/W
°C/W
Notes:
6.V
IH(MAX)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7.V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
8.Overshoot and undershoot specifications are characterized and are not 100% tested.
9.Tested initially and after design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2009
Revision
:
1.5
4/14
ESMT
AC Test Loads and Waveforms
M24L816512SA
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[10, 11, 12, 13, 14]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK
[14]
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[11, 12]
OE HIGH to High Z[11, 12]
CE LOW to Low Z[11, 12]
CE HIGH to High Z[11, 12]
BLE
/
BHE
LOW to Data Valid
BLE
/
BHE
LOW to Low Z[11, 12]
BLE
/
BHE
HIGH to High Z[11, 12]
Address Skew
-55
Min.
55[14]
55
5
55
25
5
25
5
25
55
5
10
0
5
5
5
5
Max.
Min.
70
-70
Max.
Unit
ns
ns
ns
ns
ns
ns
70
70
35
25
ns
ns
25
70
ns
ns
ns
25
10
ns
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V
to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. The internal write time of the memory is defined by the overlap of
WE
, CE = V
IL
,
BHE
and/or
BLE
= V
IL
. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates write.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2009
Revision
:
1.5
5/14
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