ESMT
PSRAM
M24L48512DA
4-Mbit (512K x 8)
Pseudo Static RAM
Features
•
•
•
•
•
•
Advanced low power architecture
High speed: 55 ns, 60 ns and 70 ns
Wide voltage range: 2.7V to 3.6V
Typical active current: 1mA @ f = 1 MHz
Low standby power
Automatic power-down when deselected
Enable (
WE
)inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O
0
through I/O
15
) is then
written into the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by asserting the
Chip Enable One ( CE1 ) and Output Enable ( OE ) inputs LOW
while forcing Write Enable (
WE
) HIGH and Chip Enable
Two(CE2) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected CE1
HIGH or CE2 LOW), the outputs are disabled ( OE HIGH), or
during write operation ( CE1 LOW, CE2 HIGH, and
WE
LOW).See the Truth Table for a complete description of read
and write modes.
Functional Description
The M24L48512DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 8 bits. Easy
memory expansion is provided by an active LOW Chip
Enable( CE1 ), an active HIGH Chip Enable (CE2), and active
LOW Output Enable ( OE ).This device has an automatic
power-down feature that reduces power consumption
dramatically when deselected. Writing to the device is
accomplished by taking Chip Enable One ( CE1 ) and Write
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2008
Revision
:
1.1
1/12
ESMT
Pin Configuration[1]
M24L48512DA
Product Portfolio
Power Dissipation
Product
Min.
V
CC
Range(V)
Speed
(ns)
Max.
55
M24L48512DA
2.7
3.0
3.6
60
70
1
5
Operating, I
CC
(mA)
f = 1 MHz
Typ.[2]
Max.
f = f
MAX
Typ.[2]
14
8
Max.
22
15
Standby, I
SB2
(µA)
Typ.[2]
Max.
Typ.
17
40
Notes:
1. NC “no connect”—not connected internally to the die.
2.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC (typ)
and T
A
= 25°C.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
2/12
ESMT
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–40°C to +85°C
Supply Voltage to Ground Potential ................−0.4V to 4.6V
DC Voltage Applied to Outputs
in High-Z State[3, 4, 5] .......................................−0.4V to 3.7V
DC Input Voltage[3, 4, 5] ....................................−0.4V to 3.7V
Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
M24L48512DA
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Extended
Industrial
Ambient Temperature (T
A
)
−25°C
to +85°C
−40°C
to +85°C
V
CC
2.7V to 3.6V
2.7V to 3.6V
Electrical Characteristics (Over the Operating Range)
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE1
Power-down
Current —CMOS
Inputs
Automatic CE1
Power-down
Current —CMOS
Inputs
Test Conditions
Min.
2.7
V
CC
– 0.4
0.4
0.8 * V
CC
-0.4
GND
≤
V
IN
≤
Vcc
GND
≤
V
OUT
≤
Vcc, Output
Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 3.6V,
I
OUT
= 0 mA,
CMOS level
-1
-1
14 for 55ns speed
14 for 60 ns speed
8 for 70 ns speed
-55, 60, 70
Typ.[2]
3.0
Max.
3.6
Unit
V
V
V
V
V
µA
µA
mA
I
OH
=
−0.1
mA
I
OL
= 0.1 mA
V
CC
+ 0.4
0.4
+1
+1
22 for 55 ns speed
22 for 60 ns speed
15 for 70 ns speed
1 for all speed
5 for all speeds
I
SB1
CE1
≥
V
CC
−
0.2V, CE2
≤
0.2V, V
IN
≥
V
CC
−
0.2V, V
IN
≤
0.2V, f = f
MAX
(Address and Data
Only),
f=0
CE1
≥
V
CC
−
0.2V, CE2
≤
0.2V, V
IN
≥
V
CC
−
0.2V or V
IN
≤
0.2V, f = 0, V
CC
= 3.6V
150
250
µA
I
SB2
17
40
µA
Capacitance[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Notes:
3.V
IH(MAX)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
4.V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
5.Overshoot and undershoot specifications are characterized and are not 100% tested.
6.Tested initially and after design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
3/12
ESMT
Thermal Resistance[6]
Parameter
θ
JA
θ
JC
M24L48512DA
Description
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
VFBGA
55
17
Unit
°C/W
°C/W
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
AC Test Loads and Waveforms
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
22000
22000
11000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics (Over the Operating Range)[7]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[8, 9]
OE HIGH to High Z[8, 9]
CE1 LOW and CE2 HIGH to Low Z[8,
9]
2
25
0
55
45
45
0
60
45
45
0
5
25
2
25
5
70
60
55
0
–55
Min.
55
[11]
55
5
55
25
5
25
5
25
10
8
60
25
5
25
Max.
Min.
60
60
10
70
35
–60
Max.
Min.
70
70
–70
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 HIGH and CE2 LOW to High Z[8,
9]
[11]
t
SK
Address Skew
Write Cycle[10]
t
WC
Write Cycle Time
t
SCE
CE1 LOW and CE2 HIGH to Write End
t
AW
t
HA
Address Set-up to Write End
Address Hold from Write End
Notes:
7. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to
V
CC(typ)
, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
9. High-Z and Low-Z parameters are characterized and are not 100% tested.
10.The internal write time of the memory is defined by the overlap of
WE
, CE1 = V
IL
, and CE2 = V
IH
. All signals must be ACTIVE
to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing
should be referenced to the edge of the signal that terminates write.
11.To achieve 55-ns performance, the read access should be CE controlled. In this case t
ACE
is the critical parameter and t
SK
is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
4/12
ESMT
Switching Characteristics (Over the Operating Range)[7] (continued)
Prameter
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Description
Address Set-up to Write Start
WE
Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE
LOW to High Z[8, 9]
WE
HIGH to Low Z[8, 9]
M24L48512DA
–55
Min.
0
40
25
0
25
5
5
Max.
Min.
0
40
25
0
25
5
–60
Max.
Min.
0
45
25
0
25
–70
Max.
Unit
ns
ns
ns
ns
ns
ns
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [11, 12, 13]
Read Cycle 2 (
OE
Controlled) [11, 13]
Notes:
12.Device is continuously selected. OE , CE = V
IL
.
13.
WE
is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
5/12
综合技术交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
