ESMT
Revision History :
Revision 1.0 (Jul. 5, 2007)
- Original
M24D816512DA
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
1/13
ESMT
PSRAM
Features
• Wide voltage range: 1.7V–1.95V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 20 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
M24D816512DA
8-Mbit (512K x 16)
Pseudo Static RAM
placed in a high-impedance state when: deselected ( CE1
HIGH or CE2 LOW), outputs are disabled ( OE HIGH), both
Byte High Enable and Byte Low Enable are disabled
(
BHE
,
BLE
HIGH), or during a write operation ( CE1 LOW
and CE2 HIGH and
WE
LOW). Writing to the device is
accomplished by taking Chip Enable( CE1 LOW and CE2
HIGH) and Write Enable (
WE
) input LOW. If Byte Low
Enable (
BLE
) is LOW, then data from I/O pins (I/O0through
I/O7), is written into the location specified on the address pins
(A0 through A18). If Byte High Enable (
BHE
) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written in to the
location specified on the address pins (A
0
through
A
18
).Reading from the device is accomplished by taking Chip
Enables ( CE1 LOW and CE2 HIGH) and Output Enable
( OE )LOW while forcing the Write Enable (
WE
) HIGH. If
Byte Low Enable (
BLE
) is LOW, then data from the memory
location specified by the address pins will appear on I/O
0
to
I/O
7
. If Byte High Enable (
BHE
) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. Refer to the truth table for
a complete description of read and write modes..
Functional Description[1]
The M24D816512DA is a high-performance CMOS Pseudo
Static RAM organized as 512K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE1 HIGH or CE2 LOW or both
BHE
and
BLE
are HIGH). The input/output pins (I/O0 through I/O
15
) are
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
2/13
ESMT
Pin Configuration[2, 3]
48-Ball VFBGA
Top View
M24D816512DA
Product Portfolio [4]
Power Dissipation
Product
Min.
M24D816512DA
1.7
V
CC
Range (V)
Speed(ns)
Max.
1.95
55
70
Operating I
CC
(Ma)
f = 1MHz
.Typ.[4]
3
Max.
5
f = fmax
.Typ.[4]
20
18
Max.
35
25
Standby ISB2(µA)
.Typ. [4]
32
Max.
70
Typ.[4]
1.8
Note:
2.Ball G2, H6 and E3 can be used to upgrade to a 16-Mbit, 32-Mbit and a 64-Mbit density, respectively.
3.NC “no connect” - not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC
(typ)
and T
A
= 25°C. Tested initially and after design changes that may affect the parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
3/13
ESMT
Power-up Characteristics
M24D816512DA
The initialization sequence is shown in Figure1. Chip Select should be CE1 HIGH or CE2 LOW for at least 200 µs after V
CC
has
reached a stable value. No access must be attempted during this period of 200 µs.
Parameter
Tpu
Description
CE1 LOW and CE2 HIGH After Stable V
CC
Min.
200
Typ.
Max.
Unit
µs
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
4/13
ESMT
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied ..............................................–55°C to +125°C
Supply Voltage to
Ground Potential . ............................−0.2V to V
CCMAX
+ 0.3V
DC Voltage Applied to Outputs
in High-Z State[5, 6, 7] ......................
−0.2V
to V
CCMAX
+ 0.3V
DC Input Voltage[5, 6, 7]....................
−0.2V
to V
CCMAX
+ 0.3V
Output Current into Outputs (LOW) ...............................20 mA
M24D816512DA
Static Discharge Voltage ........................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Operating Range
Range
Industrial
Ambient
Temperature (T
A
)
−40°C
to +85°C
V
CC
1.7V to 1.95V
DC Electrical Characteristics (Over the Operating Range)[5,6,7]
-55
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current
—CMOS Inputs
Test Conditions
Min.
I
OH
=
−0.1
mA
V
CC
= 1.7V to 1.95V
I
OL
= 0.1 mA
V
CC
= 1.7V to 1.95V
V
CC
= 1.7V to 1.95V
V
CC
= 1.7V to 1.95V
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
f = f
MAX
= 1/t
RC
f = 1 MHz
I
SB2
CE1
≥
V
CC
−0.2V
or CE2
≤
0.2V
V
IN
≥
V
CC
−
0.2V or V
IN
≤
0.2V,
f = 0, V
CC
= V
CCMAX
V
CC
= V
CCMAX
I
OUT
= 0mA
CMOS levels
2.7
V
CC
-
0.2
0.8*
V
CC
-0.2
-1
-1
20
3
32
Typ
.[4]
1.8
Max.
1.95
Min.
1.7
V
CC
-
0.2
0.8*
V
CC
-0.2
-1
-1
18
3
32
-70
Typ.
[4]
1.8
Unit
Max.
1.95
V
V
0.2
V
CC
+0.3V
0.2*
V
CC
+1
+1
25
5
40
V
V
V
µA
µA
mA
mA
µA
0.2
V
CC
+
0.3V
0.2*
V
CC
+1
+1
35
5
40
Capacitance[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance[8]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance(Junction to Ambient)
Thermal Resistance (Junction to Case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/ JESD51.
BGA
56
11
Unit
°C/W
°C/W
Notes:
5.V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
6.V
IH(Max)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7.Overshoot and undershoot specifications are characterized and are not 100% tested.
8.Tested initially and after any design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
5/13
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