ESMT
Revision History :
Revision 1.0 (Jul. 6, 2007)
- Original
M24D16161DA
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
1/12
ESMT
PSRAM
Features
• Wide voltage range: 1.7V–1.95V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
‧Available
in 48-ball BGA package
• Operating Temperature: –40°C to +85°C
M24D16161DA
16-Mbit (1M x 16)
Pseudo Static RAM
CE2 LOW), outputs are disabled ( OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (
BHE
,
BLE
HIGH), or during a write operation ( OE1 LOW and CE2
HIGH and
WE
LOW).
To write to the device, take Chip Enable ( CE1 LOW and
CE2HIGH) and Write Enable (
WE
) input LOW. If Byte Low
Enable(
BLE
) is LOW, then data from I/O pins (I/O
0
through
I/O
7
), is written into the location specified on the address pins
(A0through A
19
). If Byte High Enable (
BHE
) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written into the
location specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables ( CE1 LOW and
CE2 HIGH) and Output Enable ( OE ) LOW while forcing the
Write Enable (
WE
) HIGH. If Byte Low Enable (
BLE
) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (
BHE
) is
LOW, then data from memory will appear on I/O
8
to
I/O
15
.Refer to the truth table for a complete description of read
and write modes.
Functional Description[1]
The M24D16161DA is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal portable applications such as cellular telephones.
The device can be put into standby mode when deselected
( CE1 HIGH or CE2 LOW or both
BHE
and
BLE
are
HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in
a high-impedance state when : deselected ( CE1 HIGH or
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
2/12
ESMT
Pin Configuration[2, 3]
48-ball VFBGA
Top View
M24D16161DA
Product Portfolio[4]
Power Dissipation
Product
Min.
M24D16161DA
1.7
V
CC
Range (V)
Typ.[4]
1.8
Max
1.95
Speed(ns)
Operating I
CC
(mA)
f = 1MHz
f = fmax
.Typ.[4] Max.
.Typ.[4]
Max
3
5
18
20
Standby I
SB2
(µA)
.Typ. [4]
55
Max
70
70
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select should be OE1 HIGH or CE2 LOW for at least 200 µs
after V
CC
has reached a stable value. No access must be
attempted during this period of 200 µs.
Parameter
T
PU
Description
Chip Enable Low After Stable V
CC
Min.
200
Max.
Unit
µs
Notes:
2.Ball H6 and E3 can be used to upgrade to a 32-Mbit and a 64-Mbit density, respectively.
3.NC “no connect”-not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC (typ)
and T
A
= 25°C. Tested initially and after design changes that may affect the parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
3/12
ESMT
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential.–0.2V to V
CCMAX
+ 0.3V
DC Voltage Applied to Outputs
in High Z State[5, 6, 7]........................–0.2V to V
CCMAX
+ 0.3V
DC Input Voltage[5, 6, 7]....................–0.2V to V
CCMAX
+ 0.3V
Output Current into Outputs (LOW).............................20 mA
M24D16161DA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current....................................................> 200 mA
Operating Range
Range
Industrial
Ambient
Temperature (T
A
)
−40°C
to +85°C
V
CC
1.7V to 1.95V
DC Electrical Characteristics (Over the Operating Range) [5, 6, 7]
Parameter
V
CC
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Supply Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current
—CMOS Inputs
Automatic CE
Power-Down
Current
—CMOS Inputs
Test Conditions
Min.
1.7
I
OH
=
−0.1
mA
V
CC
= 1.7V to 1.95V
I
OL
= 0.1 mA,
V
CC
= 1.7V to 1.95V
V
CC
= 1.7V to 1.95V
V
CC
= 1.7V to 1.95V
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
f = f
MAX
= 1/t
RC
f = 1 MHz
CE
≥
V
CC
−
0.2V, CE2
≤
0.2V, V
IN
> V
CC
−
0.2V, V
IN
< 0.2V, f = f
MAX
(Address and
Data Only), f = 0
( OE ,
WE
,
BHE
and
BLE
), V
CC
=3.60V
-70
Typ.[4]
1.8
Max.
1.95
Unit
V
V
0.2
V
V
V
µA
µA
mA
mA
V
CC
-0.2
0.8* V
CC
-0.2
-1
-1
V
CC
= V
CCmax
I
OUT
= 0mA
CMOS levels
18
3
V
CC
+0.3V
0.2* V
CC
+1
+1
25
5
I
SB1
55
70
µA
I
SB2
CE1
≥
V
CC
−0.2V,
CE2
≤
0.2V, V
IN
≥
V
CC
−
0.2V or V
IN
≤
0.2V, f = 0, V
CC
=
V
CCMAX
,
55
70
µA
Capacitance[8]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance[8]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedence, per EIA/JESD51.
VFBGA
56
11
Unit
°C/W
°C/W
Notes:
5. V
IL(MIN)
= –0.5V for pulse durations less than 20 ns.
6.V
IH(Max)
= V
CC
+ 0.5V for pulse durations less than 20 ns.
7.Overshoot and undershoot specifications are characterized and are not 100% tested.
8.Tested initially and after any design or process changes that may affect these parameters.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
4/12
ESMT
AC Test Loads and Waveforms
M24D16161DA
Parameters
R1
R2
R
TH
V
TH
1.8V V
CC
14000
14000
7000
1.90
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[9, 10, 11, 15, 14]
Parameter
Read Cycle
t
RC
[13]
t
CD
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
Read Cycle Time
Chip Deselect Time CE1 =HIGH or CE2=LOW,
BLE
/
BHE
High Pulse Time
Address to Data Valid
Data Hold from Address Change
Description
-70
Min.
70
15
70
5
70
35
5
25
10
25
70
5
25
Max.
40000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[10, 11, 12]
OE HIGH to High Z[10, 11, 12]
CE1 LOW and CE2 HIGH to Low Z[10, 11, 12]
CE1 HIGH and CE2 LOW to High Z[10, 11, 12]
BLE
/
BHE
LOW to Data Valid
BLE
/
BHE
LOW to Low Z[10, 11, 12]
BLE
/
BHE
HIGH to High Z[10, 11, 12]
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of V
CC(typ.)
/2, input pulse levels of 0V to V
CC
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads
and Waveforms” section.
10. At any given temperature and voltage conditions t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and
t
HZWE
is less than t
LZWE
for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13 .If invalid address signals shorter than min. t
RC
are continuously repeated for 40 µs, the device needs a normal read timing
(t
RC
) or needs to enter standby state at least once in every 40 µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable ( CE1 or CE2) controlled. That is, the
addresses must be stable prior to Chip Enable going active.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
5/12
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