ESMT
Revision History :
Revision 1.0 (Jul. 06, 2007)
- Original
M24D16161ZA
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
1/15
ESMT
PSRAM
Features
Features
•Wide voltage range: 1.7V–1.95V
•Access Time: 70 ns
•Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
•Ultra low standby power
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Deep Sleep Mode
•Available in Lead-Free 48-ball BGA Package
•Operating Temperature: –40°C to +85°C
M24D16161ZA
16-Mbit (1M x 16)
Pseudo Static RAM
are disabled ( OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (
BHE
,
BLE
HIGH), or during a
write operation ( CE LOW and
WE
LOW).
To write to the device, take Chip Enable ( CE LOW) and
Write Enable (
WE
) input LOW. If Byte Low Enable (
BLE
) is
LOW, then data from I/O pins (I/O
0
through I/O
7
), is written
into the location specified on the address pins (A
0
through
A
19
).
If Byte High Enable (
BHE
) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
19
).To read from the device, take
Chip Enables ( CE LOW) and Output Enable ( OE ) LOW
while forcing the Write Enable (
WE
) HIGH. If Byte Low
Enable (
BLE
) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If
Byte High Enable (
BHE
) is LOW, then data from memory will
appear on I/O
8
to I/O
15
. Refer to the truth table for a complete
description of read and write modes.
Deep Sleep Mode is enabled by driving
ZZ
LOW. See the
Truth Table for a complete description of Read, Write, and
Deep Sleep mode.
Functional Description[1]
The M24D16161ZA is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both
BHE
and
BLE
are HIGH).
The input/output pins (I/O0through I/O
15
) are placed in a
high-impedance state when: deselected ( CE HIGH), outputs
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
2/15
ESMT
Pin Configuration[2, 3]
48-ball VFBGA
Top View
M24D16161ZA
Product Portfolio
Product
M24D16161ZA
Min.
1.7
V
CC
Range (V)
Typ.
1.8
Max.
1.95
Speed(ns)
70
Power Dissipation
Operating I
CC
(mA)
Standby I
SB2
(µA)
f = 1MHz
f = f
MAX
Typ.[4]
Max.
Typ.[4]
Max.
Typ. [4]
Max.
3
5
18
20
55
70
Stand-By Mode, as configured by the user through the
settings in the Variable Address Register.
Once
ZZ
returns high in this mode, the PSRAM goes back
too perating in full address refresh. Please refer to “Variable
Address Space Register (VAR)” on page4 for the protocol to
turn off sections of the memory in Stand-By mode. If the VAR
register is not updated after the power up, the PSRAM will be
in its default state. In the default state the whole memory
array will be refreshed in the Stand-By Mode. The 16-Mbit is
divided into four 4-Mbit sections allowing certain sections to
be active (i.e., refreshed).
Deep Sleep Mode
In this mode, the data integrity in the PSRAM is not
guaranteed. This mode can be used to lower the power
consumption of the PSRAM in an application. This mode can
be enabled and disabled through VAR similar to the RMS and
PAR mode. Deep Sleep Mode is activated by driving
ZZ
LOW. The device stays in the deep sleep mode until
ZZ
is
driven HIGH.
Low-Power Modes
At power-up, all four sections of the die are activated and the
PSRAM enters into its default state of full memory size and
refresh space. This device provides four different Low-Power
Modes.
1.Reduced Memory Size Operation
2.Partial Array Refresh
3.Deep Sleep Mode
4.Temperature Controlled Refresh
Reduced Memory Size Operation
In this mode, the 16 Mb PSRAM can be operated as a
12-Mbit,8-Mbit or a 4-Mbit memory block. Please refer to
“Variable Address Space Register (VAR)” on page4 for the
protocol to turn on/off sections of the memory. The device
remains in RMS mode until changes to the Variable Address
Space register are made to revert back to a complete 16-Mbit
PSRAM.
Partial Array Refresh
The Partial Array Refresh mode allows customers to turn off
sections of the memory block in the Stand-by mode (with
ZZ
tied low) to reduce standby current. In this mode the PSRAM
will only refresh certain portions of the memory in the
Notes:
2.Ball H6, E3 can be used to upgrade to 32M and 64M density respectively.
3.NC “no connect” - not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
,
T
A
= 25°C. Tested initially and after any design changes that may affect the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
3/15
ESMT
Variable Address Mode Register (VAR) Update[5, 6]
M24D16161ZA
Deep Sleep Mode—Entry/Exit [7]
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter
t
ZZWE
t
CDR
t
R
[7]
t
ZZMIN
Notes:
5. OE and the data pins are in a don’t care state while the device is in variable address mode.
6.All other timing parameters are as shown in the data sheets.
7.t
R
applies only in the deep sleep mode.
Description
ZZ
LOW to Write Start
Min.
Max.
1
Unit
µs
ns
µs
µs
Chip deselect to
ZZ
LOW
Operation Recovery Time (Deep Sleep Mode only)
Deep Sleep Mode Time
0
200
8
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
4/15
ESMT
Variable Address Space Register (VAR)
M24D16161ZA
Variable Address Space—Address Patterns
Partial Array Refresh Mode (A3 = 0, A4 = 1)
A2
0
0
0
1
1
1
A1,A0
1 1
1 0
0 1
1 1
1 0
0 1
Refresh Section
1/4
th
of the array
1/2
th
of the array
3/4
th
of the array
1/4
th
of the array
1/2
th
of the array
3/4
th
of the array
1/4
th
of the array
1/2
th
of the array
3/4
th
of the array
Full array
1/4
th
of the array
1/2
th
of the array
3/4
th
of the array
Full array
Address
00000h-3FFFFh (A19 = A18 = 0)
00000h-7FFFFh (A19 = 0)
00000h-BFFFFh (A19:A18 not equal to 1 1)
C0000h-FFFFFh (A19 = A18= 1)
80000h-FFFFFh (A19 = 1)
40000h-FFFFFh (A19:A18 not equal to 0 0)
Reduced Memory Size Mode (A3 = 1, A4 = 1)
0
0
0
0
1
1
1
1
1 1
1 0
0 1
0 0
1 1
1 0
0 1
0 0
00000h-3FFFFh (A19 = A18 = 0)
00000h-7FFFFh (A19 = 0)
00000h-BFFFFh (A19:A18 not equal to 1 1)
00000h-FFFFFh (Default)
C0000h-FFFFFh (A19 = A18 = 1)
80000h-FFFFFh (A19 = 1)
40000h-FFFFFh (A19:A18 not equal to 0 0)
00000h-FFFFFh (Default)
256K x 16
512K x 16
768K x 16
1M x 16
256K x 16
512K x 16
768K x 16
1M x 16
4M
8M
12M
16M
4M
8M
12M
16M
Size
256K x 16
512K x 16
768K x 16
256K x 16
512K x 16
768K x 16
Density
4M
8M
12M
4M
8M
12M
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jul. 2007
Revision
:
1.0
5/15
瑞萨MCU/MPU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
