ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
, V
DDQ
= 2.5V ~ 2.7V
Auto & Self refresh
7.8us refresh interval (64ms refresh period, 8K cycle)
SSTL-2 I/O interface
66pin TSOPII package
M13S5121632A
8M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Ordering information:
PRODUCT ID
M13S5121632A -5TG
MAX FREQ
200MHz
VDD
2.5V
PACKAGE
TSOPII
COMMENTS
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
1/47
ESMT
Functional Block Diagram
M13S5121632A
DQ0 - 15
UDQS, LDQS
DLL
I/O Buffer
DQS Buffer
Memory
Array
Bank#0
Memory
Array
Bank#1
Memory
Array
Bank#2
Memory
Array
Bank#3
Mode Register
Control Circuitry
Address Buffer
Clock Buffer
A0-12
BA0,1
CLK
CLK
CKE
Control Signal Butter
CS
RAS CAS WE
DM
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
2/47
ESMT
Pin Arrangement
M13S5121632A
x1 6
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x 16
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CLK
CLK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
Pin Description
Pin Name
Function
Address inputs
- Row address A0~A12
- Column address A0~ A9
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
Pin Name
Function
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL-2
A0~A12,
BA0,BA1
LDM, UDM
DQ0~DQ15
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
NC
V
SS
V
DD
LDQS, UDQS
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
3/47
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SSQ
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ V
DDQ
+ 0.5
-0.5 ~ 3.7
-0.5 ~ 3.7
-55 ~ +150
1500
50
M13S5121632A
Unit
V
V
V
°C
mW
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= 0 to 70 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
I
OH
I
OL
Min
2.5
2.5
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
-2
-5
-16.2
+16.2
Max
2.7
2.7
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.15
V
DDQ
+ 0.3
V
DDQ
+ 0.6
2
5
Unit
V
V
V
V
V
V
V
V
3
1
2
Note
μ
A
μ
A
mA
mA
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set equal
to V
REF
, and must track variations in the DC level of V
REF
.
3. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
4/47
ESMT
DC Specifications
Parameter
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
Idle Standby Current
Active Power-down
Standby Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
Operation Current
(Four Bank Operation)
Symbol
IDD0
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Test Condition
t
RC
= t
RC
(min), t
CK
= t
CK
(min), Active – Precharge
Burst Length = 2, t
RC
= t
RC
(min), CL= 2.5,
I
OUT
= 0mA, Active-Read- Precharge
CKE
≤
V
IL
(max), t
CK
= t
CK
(min), All banks idle
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CK
= t
CK
(min)
All banks ACT, CKE
≤
V
IL
(max), t
CK
= t
CK
(min)
One bank; Active-Precharge, t
RC
= t
RAS
(max),
t
CK
= t
CK
(min)
Burst Length = 2, CL= 2.5, t
CK
= t
CK
(min), I
OUT
= 0 mA
Burst Length = 2, CL= 2.5, t
CK
= t
CK
(min)
t
RC
≥
t
RFC
(min)
CKE
≤
0.2V
Four bank interleaving with BL=4, t
RC
= t
RC
(min),
burst mode; Read with auto precharge;
Address and control inputs on NOP edge are not
changing. I
OUT
= 0 mA
M13S5121632A
Version
-5
180
210
10
55
45
60
460
360
290
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
Unit
Note
IDD7
630
mA
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note 1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 2.5V~2.7V, V
DDQ
= 2.5V~2.7V, T
A
= 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
2.0
2.0
4.0
4.0
Max
3.5
3.5
5.0
5.0
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
5/47
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