ESMT
Revision History
Revision 1.0 (Dec. 14 2007)
-Original
M13S128324A
Operation Temperature Condition -40~85°C
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
1/49
ESMT
DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3;4
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, full page
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.625V, V
DDQ
= 2.375V ~ 2.625V
Auto & Self refresh
32ms refresh period (4K cycle)
SSTL-2 I/O interface
144Ball FBGA and 100 pin LQFP package
M13S128324A
Operation Temperature Condition -40~85°C
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Operating Frequencies :
PRODUCT NO.
M13S128324A -5BIG
M13S128324A -6BIG
M13S128324A -5LIG
M13S128324A -6LIG
MAX FREQ
200MHz
166MHz
200MHz
166MHz
VDD
2.5V
2.5V
2.5V
2.5V
PACKAGE
144 Ball FBGA
144 Ball FBGA
100 pin LQFP
100 pin LQFP
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
2/49
ESMT
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
M13S128324A
Operation Temperature Condition -40~85°C
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
CS
RAS
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Refresh
Counter
DM
Column Decoder
DQ
CLK, CLK
DLL
DQS
DQS
Pin Arrangement
144(12x12) FBGA
2
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
3
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
4
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
5
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA1
A0
6
DQ2
DQ1
VSSQ
VSSQ
VSS
Thermal
7
DQ0
VDDQ
VDD
VSS
VSS
Thermal
8
DQ31
VDDQ
VDD
VSS
VSS
Thermal
9
DQ29
DQ30
VSSQ
VSSQ
VSS
Thermal
10
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
A7
11
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CK
A8/AP
12
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
CK
CKE
13
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
NC
VREF
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
A10
A2
A1
VSS
VDD
NC
A11
A3
VSS
VDD
A9
A4
VSS
NC
A5
A6
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
3/49
ESMT
Pin Arrangement
M13S128324A
Operation Temperature Condition -40~85°C
DQ29
V
SSQ
DQ30
DQ31
V
SS
V
DDQ
N.C
N.C
N.C
N.C
N.C
V
SSQ
N.C
DQS
V
DDQ
V
DD
DQ0
DQ1
V
SSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
A
7
A
6
A
5
A
4
V
SS
A
9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A11
A10
V
DD
A
3
A
2
A
1
A
0
100 Pin LQFP
Forward Type
20 x 14 mm
0.65 mmpin Pitch
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Pin Description
(M13S128324A)
Pin Name
Function
Address inputs
- Row address A0~A11
- Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~DQ7.
DQS1 correspond to the data on DQ8~DQ15.
DQS2 correspond to the data on DQ16~DQ23.
DQS3 correspond to the data on DQ24~DQ31.
Bi- directional Data Strobe.
Pin Name
Function
A0~A11,
BA0,BA1
DM0~DM3
DQ Mask enable in write cycle.
DQ0~DQ31
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
V
REF
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL
V
SS
V
DD
DQS0~DQS3
(for FBGA)
DQS
(for LQFP)
NC
No connection
-
-
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
4/49
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
2
50
M13S128324A
Operation Temperature Condition -40~85°C
Unit
V
V
V
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= -40 to 85 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
Output High Current (Weak strength driver)
(V
OUT
=V
DDQ
-0.763V, min V
REF
, min V
TT
)
Output Low Current (Weak strength driver)
(V
OUT
= 0.763V)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.375
2.375
0.49*V
DDQ
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-5
-5
-16.8
+16.8
-9
+9
Max
2.625
2.625
0.51*V
DDQ
V
REF
+ 0.04
V
DDQ
+ 0.3
V
REF
- 0.15
5
5
Unit
V
V
V
V
V
V
1
2
Note
μ
A
μ
A
mA
mA
mA
mA
3
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2.
V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set
equal to V
REF
, and must track variations in the DC level of V
REF
.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.0
5/49
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