ESMT
SDRAM
M12L128168A
2M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
Burst Read single write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
PRODUCT NO.
M12L128168A-5TG
M12L128168A-5BG
M12L128168A-6TG
M12L128168A-6BG
M12L128168A-7TG
M12L128168A-7BG
MAX FREQ. PACKAGE
200MHz
200MHz
166MHz
166MHz
143MHz
143MHz
54 TSOP II
54 Ball FBGA
54 TSOP II
54 Ball FBGA
54 TSOP II
54 Ball FBGA
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
1/45
ESMT
BLOCK DIAGRAM
CLK
CKE
Address
Mode
Register
Clock
Generator
Bank D
Bank C
Bank B
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
M12L128168A
Bank A
Sense Amplifier
Command Decoder
Control Logic
L(U)DQM
CS
RAS
CAS
WE
Column
Address
Buffer
&
Counter
Column Decoder
Input & Output
Buffer
Latch Circuit
Data Control Circuit
DQ
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A11
BA0 , BA1
RAS
NAME
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
INPUT FUNCTION
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
CAS
WE
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
L(U)DQM
DQ0 ~ DQ15
V
DD
/ V
SS
V
DDQ
/ V
SSQ
N.C
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
2/45
ESMT
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Note :
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
TSTG
PD
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
M12L128168A
Unit
V
V
°
C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
°
C )
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note:
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
μ
A
Note
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
μ
A
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL(min)
= -1.5V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
, all other pins are not under test = 0V.
4. Dout is disabled , 0V
≤
V
OUT
≤
V
DD.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°
C , f = 1MHZ)
Parameter
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
& L(U)DQM)
Data input/output capacitance (DQ0 ~ DQ15)
C
OUT
2
6.5
pF
Symbol
C
IN1
C
IN2
Min
2.5
2.5
Max
4
4
Unit
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
3/45
ESMT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T
A
= 0 to 70
°
C
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Symbol
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
Active Standby Current
in power-down mode
I
CC3P
I
CC3PS
Test Condition
M12L128168A
Version
-5
-6
160
2
2
45
-7
140
Unit
mA
mA
Note
1,2
Burst Length = 1, t
RC
≥
t
RC(min)
, I
OL
= 0 mA
CKE
≤
V
IL
(max), tcc = t
CK(MIN)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH(min)
, CS
≥
V
IH(min)
, t
CC
= t
CK(MIN)
Input signals are changed one time during 2t
ck
CKE
≥
V
IH(min)
, CLK
≤
V
IL
(max), tcc =
∞
input signals are stable
CKE
≤
V
IL
(max), t
CC
= t
CK(MIN)
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
170
Precharge Standby Current
in non power-down mode
mA
25
6
6
mA
55
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3N
Input signals are changed one time during 2clks
All other pins
≥
V
DD
-0.2V or
≤
0.2V
I
CC3NS
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note :
I
CC4
I
CC5
I
CC6
CKE
≥
V
IH(min)
, CLK
≤
V
IL
(max), t
CC
=
∞
input signals are stable
I
OL
= 0 mA, Page Burst, 2 Banks activated
t
RC
≥
t
RC(min)
CKE
≤
0.2V
280
280
35
210
210
2
180
180
mA
mA
mA
mA
1,2
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
4/45
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V
，
T
A
= 0 to 70
°
C
)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
M12L128168A
Unit
V
V
ns
V
3.3V
1200
Output
870
Ω
50pF
Vtt = 1.4V
Ω
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
Z0 =50
50
Ω
Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
@ Operating
Row cycle time
@ Auto refresh
Symbol
-5
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC(min)
t
RFC(min)
t
CDL(min)
t
RDL(min)
t
BDL(min)
t
BEF(max)
53
55
10
15
15
38
Version
-6
12
18
18
40
100
58
60
1
2
1
64
63
70
-7
14
20
20
42
ns
ns
ns
ns
us
ns
ns
t
CK
t
CK
t
CK
ms
1
1,5
2
2
2
6
1
1
1
1
Unit
Note
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Refresh period (4,096 rows)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
5/45
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