AFBR-5978Z
Digital Diagnostic 650nm Transceiver for Fast Ethernet
(10/100 Mbps) with SC-RJ connector
Data Sheet
Description
The AFBR-5978Z transceiver provides the system de-
signer with the ability to implement Fast Ethernet (100
Mbps) or Ethernet (10 Mbps) over 50 meter standard
bandwidth 0.5±0.05 NA POF and 100 meter standard
bandwidth 0.37±0.04 NA HCS fiber. The connectivity
available for the transceiver is SC-RJ. This product is lead
free and compliant with RoHS.
Features
•
Compatible with electrical and optical performance
of the POFAC recommendations for the Fast Ethernet
over Plastic Optical Fiber (POF).
•
Compatible with the Electrical and Optical perfor-
mance of the ProfiNet recommendations the Fast
Ethernet over POF and Hard-Clad Silica Fiber (HCS).
•
Manufactured in an ISO 9001 certified facility
•
DMI [Digital Diagnostics Monitoring Interface,
SFF-8472 Rev 9.3], provides real-time monitoring of:
-
Temperature
-
Supply voltage
-
Received Optical Power (Alarm/Warning flag)
•
LVPECL Signal Detect Output
•
Temperature range –25 to +85 °C
Transmitter
The transmitter contains a 650nm LED with an integrat-
ed driver. The LED driver operates at 3.3 V. It receives a
LVPECL compatible electrical input, and converts it into
a modulated current driving the LED. The LED is pack-
aged in an optical subassembly, part of the transmitter
section. The optical subassembly couples the output
optical power efficiently into POF or HCS fiber.
Applications
•
Factory automation at Fast Ethernet speeds
•
Fast Ethernet networking over POF and HCS
•
Link Distance up to 50 m POF or 100 m HCS
(See application note 5290 for details)
HCS® is a trademark of OFS Corporation
AFBR-5978Z is compatible with the SC-RJ Connecting System from
Reichle & De-Massari AG, Switzerland
Receiver
The receiver utilizes a Si PIN photodiode. The PIN pho-
todiode is packaged in an optical sub-assembly, part of
the receiver section. This optical subassembly couples
the optical power efficiently from POF or HCS fiber to
the receiving PIN. The integrated IC operates at 3.3 V and
converts the photocurrent into LVPECL compatible elec-
trical output.
Package
The transceiver package consist of four basic elements;
two optical subassemblies, an electrical subassembly
and the housing as illustrated in the block diagrams in
Figure 1. The package outline drawing and pin out are
shown in Figures 2 and 3.
Patent -
www.avagotech.com/patents
Block diagram
ELECTRICAL SUBASSEMBLY
DIFFERENTIAL
DATA OUT
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DMI
DIFFERENTIAL
DATA IN
DRIVER IC
SC-RJ
RECEPTACLE
PIN PHOTODIODE
LED
TOP VIEW
Figure 1. Block diagram
The optical subassemblies utilize a high volume assem-
bly process together with low cost lens elements which
result in a cost effective building block.
The electrical subassembly consists of a high volume
multilayer printed circuit board on which the IC chips
and various surface mounted passive circuit elements
are attached.
The housing includes internal shields for the electri-
cal and optical subassemblies to insure low EMI emis-
sions and high immunity to external EMI fields. The
outer housing including the duplex SC-RJ connector is
molded of filled non-conductive plastic to provide me-
chanical strength and electrical isolation. The low profile
of the Avago Technologies transceiver design complies
with the maximum height allowed for the duplex SC-RJ
connector over the entire length of the package.
The transceiver is attached to a printed circuit board
with twelve signal pins and the two solder posts, which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand
the mechanical loads imposed on the transceiver by
mating with the SC-RJ connectored fiber cables. The
solder posts are isolated from the circuit design of the
transceiver and do not require connection to a ground
plane on the circuit board
Figure 2. Package outline drawing.
2
Pin Descriptions
Pin 1 Sda: the data line of the two wire serial interface.
This data line should be pulled up with a 4.7k–10kΩ re-
sistor on the host board to a supply of 3.3V ±10%.
Pin 2 Rx GND: receiver ground pin. Directly connect this
pin to the receiver ground plane of the host board.
Pin 3 Rx Vcc: receiver power supply pin. Provide +3.3 V
DC via a receiver power supply filter circuit. Locate the
power supply filter circuit as close as possible to the Vcc
Rx pin.
Pin 4 Sd: signal detect pin. If an optical signal is present
at the input of the receiver, Sd output is a logic “1”.
Absence of an optical signal to the receiver results in a
logic “0” output. This signal detect output can be used
to drive a LVPECL input on an upstream circuit, such as
Signal Detect input or Loss of Signal–bar. Proper LVPECL
termination should be in place. See figure 4.
Pin 5 Rdata-: receiver data out bar. This data line is a 3.3V
LVPECL compatible differential line which should be
properly terminated with a 130Ω pull up to Vcc and 82Ω
pull down to ground.
Pin 6 Rdata+: receiver data out. This data line is a 3.3V
LVPECL compatible differential line which should be
properly terminated with a 130Ω pull up to Vcc and 82Ω
pull down to ground.
SC-RJ connector
Pin 7 Tx Vcc: transmitter power supply. Provide +3.3V DC
via a transmitter power supply filter circuit. Locate the
power supply filter circuit as close as possible to the Vcc
Tx pin.
Pin 8 Tx GND: transmitter ground. Directly connect this
pin to the transmitter ground plane on the host board.
Pin 9 Txdis: transmitter disable input. This input is used
to shut down the transmitter light output. It is internally
pulled up with a ~8 kΩ resistor.
Low (0-0.8 V) - transmitter on
Between (0.8-2.0 V) - undefined
High (2.0-3.63 V) – transmitter off
Open – transmitter off
Pin 10 Tdata+: transmitter data in. This data line is an AC
coupled 100Ω differential line which does not need any
termination at the user SERDES. The AC coupling is done
inside the module and therefore not required on the
host board.
Pin 11 Tdata-: transmitter data in bar. This data line is an
AC coupled 100Ω differential line which does not need
any termination at the user SERDES. The AC coupling is
done inside the module and therefore not required on
the host board.
Pin 12 Scl: the clock line of the two wire serial interface.
This data line should be pulled up with a 4.7k – 10 kΩ
resistor on the host board to a supply of 3.3V ±10%.
Scl
Tdata-
Tdata+
Txdis
TxGND
TxVcc
Sda
RxGND
RxVcc
Sd
Rdata-
Rdata+
bottom view
Figure 3. Pin Out diagram
3
V cc 3.3V
10µF
0.1µF
1µH
0.1µF
1µH
Protocol IC & SERDES
Tx disable
TD+
TD-
V cc 3.3V
130
130
Z = 50
Ω
Z = 50
Ω
82
82
10µF
0.1µF
Z = 50
Ω
Z = 50
Ω
Txdis
10nF
TxVcc
AFBR-5978Z
Tdata+
LED driver
10nF
RD+
RD-
Tdata-
RxVcc
Rdata+
Rdata-
Sd
100
Amplifier &
Quantisizer
PC Master
Signal Detect
82
4.7k-10k 4.7k-10k
V cc 3.3V
130
V cc 3.3V
Sda
Scl
EEPROM
Figure 4. Recommended termination circuit.
Board Layout – Decoupling Circuit and Ground Planes
It is important to take care in the layout of your circuit
board to achieve optimum performance from the trans-
ceiver. A power supply decoupling circuit is recom-
mended to filter out noise to assure optimal product
performance. It is further recommended that a contigu-
ous ground plane be provided in the circuit board di-
rectly under the transceiver to provide a low inductance
ground for signal return current. This recommendation
is in keeping with good high frequency board layout
practices.
Functional Data I/O
The LVPECL receiver output of the Avago Technologies
transceiver can be DC-coupled to the LVPECL compli-
ant network interface through a Thèvenin equivalent
transformation. For a 3.3V power supply the LVPECL
outputs should be pulled up to Vcc with a 130Ω resistor
and pulled down to ground with an 82Ω resistor. Both
coupling resistors are preferably placed close to the
network interface IC, see figure 4. AC-coupling can be
used for systems in which the transceiver and connected
logic are at different supply voltages. For AC coupling,
the coupling capacitor should be large enough to avoid
excessive low-frequency droop when the data signal
contains long strings of consecutive identical digits. The
LVPECL outputs have to be pulled down to ground first
to DC bias the output before AC coupling. Because the
LVPECL output common-mode voltage is fixed at Vcc
– 1.3V, the DC-biasing resistor can be selected by as-
suming 14 mA DC current. This results in a bias-resistor
value of 142Ω - 200Ω. After the AC-coupling capacitors,
a Thèvenin equivalent transformation connects to the
LVPECL compatible network interface, equal to the one
used in DC-coupling.
4
Digital Diagnostics Monitoring Interface
The AFBR-5978Z transceiver features an enhanced
digital diagnostic interface, compliant to the “Digital Di-
agnostic Monitoring Interface for Optical Transceivers”
SFF-8472 Multi-source Agreement (MSA). Please refer to
the MSA document to access information on the range
of options, both hardware and software, available to the
host system for exploiting the available digital diagnos-
tic features.
The enhanced digital interface allows real-time access
to device operating parameters, and includes optional
digital features such as soft control and monitoring of
I/O signals. In addition, it fully incorporates the func-
tionality needed to implement digital alarms and warn-
ings, as defined by the SFF-8472 MSA. With the digital
diagnostic monitoring interface, the user has capability
of performing component monitoring, fault isolation
and failure prediction in their transceiver-based applica-
tions.
2 wire address 1010000X (A0h)
0
Serial ID De ned by
SFP MSA (96 bytes)
95
Vendor Speci c
(32 bytes)
127
2 wire address 1010001X (A2h)
0
Alarm and Warning
Thresholds (56 bytes)
55
Cal Constants
(40 bytes)
The diagnostic monitoring interface (DMI) has two 256
byte memory maps in EEPROM which are accessible
over a two wire interface: the serial ID memory map
at address 1010000X (0xA0) and the digital diagnostic
memory map at address 1010001X (0xA2).
The serial ID memory map contains a serial identifica-
tion and vendor specific information and is read only.
The digital diagnostic memory map contains device
operating parameters and alarm and warning flags. The
operating parameters are to be retrieved through a se-
quential read command ensuring that the MSB and LSB
of each parameter are “coherent”. Furthermore, it con-
tains 120 bytes that can be written by the user as well as
a writable soft control byte.
Tables 1 to 6 detail memory contents, timing character-
istics, soft commands and alarm/warning flags.
Time Diagnostic
Interface (24 bytes)
119
127
Vendor Speci c (8 bytes)
Reserved in SFP
MSA (128 bytes)
User Writable
EEPROM (120 bytes)
247
255
255
Vendor Speci c (8 bytes)
Figure 5. Digital diagnostic memory map – specific data field description
(from SFF-8472 MSA)
5
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