DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7218xxx
Module Configuration
V/I Part Number
VR5Vx647218EBP
VR5Vx647218EBS
VR5Vx647218EBW
VR5Vx647218EBZ
VR5Vx647218EBY
VR5Vx287218EBP
VR5Vx287218EBS
VR5Vx287218EBW
VR5Vx287218EBZ
VR5Vx287218EBY
VR5Vx287218FBP
VR5Vx287218FBS
VR5Vx287218FBW
VR5Vx287218FBZ
VR5Vx287218FBY
VR5Vx567218FBP
VR5Vx567218FBS
VR5Vx567218FBW
VR5Vx567218FBZ
VR5Vx567218FBY
VR5Vx127218GBP
VR5Vx127218GBS
VR5Vx127218GBW
VR5Vx127218GBZ
Notes:
VA = Address Parity
VR = No Address Parity
Capacity
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
Module
Configuration
64Mx72
64Mx72
64Mx72
64Mx72
64Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
512Mx72
Device
Configuration
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
Device
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Module
Ranks
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
2
2
2
2
Performance
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
CAS
Latency
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
*Preliminary
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 1.8V
±
0.1V Power Supply
Registered inputs with one-clock delay
CAS Latency: CL 3, 4, 5, 6
Burst Length (4, 8)
Burst type (Sequential & Interleave)
Auto & Self-Refresh.
8k/64ms Refresh Period.
Differential CLK (/CLK) input.
Supports duplicate output strobe (RDQS, /RDQS)
On-die termination (ODT)
Off-chip driver (OCD) impedance calibration
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7218xxx Revision C Created By: Brian Ouellette
Page 1 of 17
DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7218xxx
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Front
Side
VREF
VSS
DQ0
DQ1
VSS
/DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
/DQS1
DQS1
VSS
/RESET
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Back
Side
VSS
DQ4
DQ5
VSS
DQS9
DM0
/DQS9
NC
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DQS10
DM1
/DQS10
NC
VSS
RFU
RFU
VSS
DQ14
DQ15
VSS
DQ20
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Front Side
DQ19
VSS
DQ24
DQ25
VSS
/DQS3
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
/DQS8
DQS8
VSS
CB2
CB3
VSS
VDDQ
CKE0
VDD
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Side
VSS
DQ28
DQ29
VSS
DQS12
DM3
/DQS12
NC
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DQS17
DM8
/DQS17
NC
VSS
CB6
CB7
VSS
VDDQ
**CKE1
VDD
***A15
††A14
VDDQ
A12
A9
VDD
A8
A6
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Front Side
A4
VDDQ
A2
VDD
VSS
VSS
VDD
‡PAR_IN
VDD
A10/AP
BA0
VDDQ
/WE
/CAS
VDDQ
**/S1
**ODT1
VDDQ
VSS
DQ32
DQ33
VSS
/DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
Pin
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Back Side
VDDQ
A3
A1
VDD
CK0
/CK0
VDD
A0
VDD
BA1
VDDQ
/RAS
/S0
VDDQ
ODT0
A13
VDD
VSS
DQ36
DQ37
VSS
DQS13
DM4
/DQS13
NC
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Front Side
VSS
/DQS5
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
SA2
NC
VSS
/DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
/DQS7
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
Side
DQS14
DM5
/DQS14
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
†/S2
†/S3
VSS
DQS15
DM6
/DQS15
NC
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS16
DM7
/DQS16
NC
VSS
DQ62
DQ63
VSS
VDDSPD
SA0
SA1
DQ21
54
*BA2
VSS
55 ‡ERR_OUT
DQS11
26
VSS
146
56
VDDQ
DM2
/DQS11
27
/DQS2
147
57
A11
NC
28
DQS2
148
VSS
58
A7
29
VSS
149
DQ22
59
VDD
30
DQ18
150
DQ23
60
A5
*Pins are used for 1Gbit based module
**Pins are used for dual/quad rank module
***Pins are used on modules with Address Parity
†Pins are used for quad rank module
††Pins are used for 2Gb based module
‡Pins are used on Address Parity module only
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7218xxx Revision C Created By: Brian Ouellette
Page 2 of 17
DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7218xxx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
/CK0
TYPE
IN
IN
POLARITY
DESCRIPTION
Positive Edge
Negative Edge
CKE0 ~ CKE1
IN
Active High
/S0 ~ /S3
IN
Active Low
ODT0 ~ ODT1
/RAS, /CAS, /WE
VREF
VDD
BA [2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A [n:0]
IN
-
Positive line of the differential pair of system clock inputs that drives
input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives
the input to the on-DIMM PLL.
CKE HIGH activates, and CKE LOW deactivates internal clock signals,
and device input buffers and output drivers of the SDRAMs. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and
disables decoder when high. When decoder is disabled, new
commands are ignored and previous operations continue. These input
signals also disable all outputs (except CKE and ODT) of the register(s)
on the DIMM when both inputs are high. When both S[0:1] are high, all
register outputs (except CKE, ODT and Chip select) remain in the
previous state. For modules supporting 4 ranks, S[2:3] operate similarly
to S[0:1] for a second set of register outputs.
On-Die Termination control signals
CAS, WE When sampled at the positive rising edge of the clock, /CAS,
/RAS, and /WE define the operation to be executed by the SDRAM.
Reference voltage for SSTL18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide
improved noise immunity
Selects which SDRAM bank of four or eight is activated.
During a Bank Activate command cycle, Address defines the row
address. During a Read or Write command cycle, Address defines the
column address. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2
defines the bank to be precharged. If AP is low, autoprecharge is
disabled. During a Precharge command cycle, AP is used in
conjunction with BA0, BA1,BA2 to control which bank(s) to precharge. If
AP is high, all banks will be precharged regardless of the state of BA0
or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define
which bank to precharge.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Positive line of the differential data strobe for input and output data.
Masks write data when high, issued concurrently with input data. If
RDQS is enabled, DQS9 ~ DQS17 are used in lieu of DM0 ~ DM8
DQ [63:0],
CB [7:0]
VDD, VSS
DQS [8:0]
DM [8:0]
DQS [17:9]
I/O
Supply
I/O
IN
I/O
-
-
Positive Edge
Active High
Positive Edge
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7218xxx Revision C Created By: Brian Ouellette
Page 3 of 17
DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7218xxx
PIN FUNCTION DESCRIPTION
SYMBOL
/DQS [17:0]
SA [2:0]
SDA
TYPE
I/O
IN
I/O
POLARITY
Negative Edge
-
-
DESCRIPTION
SCL
IN
-
VDDSPD
Supply
-
/RESET
Par_In
Err_Out
IN
IN
OUT
Negative line of the differential data strobe for input and output data. If
RDQS is enabled, /DQS9 ~ /DQS17 are used only during READ
command
These signals are tied at the system planar to either VSS or VDDSPD
to configure the serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. A resistor must be connected from the SDA bus line to
VDDSPD on the system planar to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A
resistor may be connected from the SCL bus time to VDDSPD on the
system planar to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin
at the connector which supports from 1.7 Volt to 3.6 Volt (nominal 1.8
Volt, 2.5 Volt and 3.3 Volt) operations.
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When low, all register outputs will be driven low and
the PLL clocks to the DRAMs and register(s) will be set to low level (the
PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Parity error found in the Address and Control bus
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7218xxx Revision C Created By: Brian Ouellette
Page 4 of 17
DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7218xxx
MECHANICAL OUTLINE SINGLE RANK
Dimensions are in inches. (Tolerance is +/- 0.005, unless otherwise stated.)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7218xxx Revision C Created By: Brian Ouellette
Page 5 of 17
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