BLF7G10L-250;
BLF7G10LS-250
Power LDMOS transistor
Rev. 6 — 7 November 2016
Product data sheet
1. Product profile
1.1 General description
250 W LDMOS power transistor for base station applications at frequencies from
869 MHz to 960 MHz.
Table 1.
Typical performance
Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF per carrier;
carrier spacing = 5 MHz. Typical RF performance at T
case
= 25
C.
Test signal
2-carrier W-CDMA
2-carrier W-CDMA
[1]
[2]
f
(MHz)
869 to 894
[1]
920 to 960
[2]
I
Dq
(mA)
1800
1800
V
DS
(V)
30
30
P
L(AV)
(W)
60
60
G
p
(dB)
19.5
19.5
D
(%)
27.4
30.5
ACPR
(dBc)
35.6
34
In a common source class-AB application test circuit.
In a common source class-AB production test circuit.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low thermal resistance providing excellent thermal stability
Designed for broadband operation (869 MHz to 960 MHz)
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use (input and output)
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for W-CDMA base stations and multi carrier applications in the
869 MHz to 960 MHz frequency range
BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
Pinning
Description
drain
gate
source
[1]
Simplified outline
Graphic symbol
BLF7G10L-250 (SOT502A)
1
3
2
1
2
3
sym112
BLF7G10LS-250 (SOT502B)
1
2
3
drain
gate
source
[1]
1
3
2
1
2
3
sym112
[1]
Connected to flange
3. Ordering information
Table 3.
Ordering information
Package
Name Description
BLF7G10L-250
BLF7G10LS-250
-
-
flanged ceramic package; 2 mounting holes; 2 leads
earless flanged ceramic package; 2 leads
Version
SOT502A
SOT502B
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
0.5
65
-
Max
65
+13
+150
200
Unit
V
V
C
C
5. Thermal characteristics
Table 5.
R
th(j-c)
Thermal characteristics
Conditions
Typ
Unit
thermal resistance from junction to case T
case
= 80
C;
P
L
= 60 W (CW);
V
DS
= 30 V; I
Dq
= 1800 mA
0.38 K/W
Symbol Parameter
BLF7G10L-250_7G10LS-250
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2016
2 of 13
BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
Conditions
V
DS
= 10 V; I
D
= 330 A
V
DS
= 30 V; I
D
= 1.8 A
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 11.55 A
Min
65
1.50
1.63
-
-
-
-
-
Typ
-
1.9
2.03
-
56
-
22
57
Max
-
2.30
2.43
5
-
0.5
-
-
Unit
V
V
V
A
A
mA
S
m
V
(BR)DSS
drain-source breakdown voltage V
GS
= 0 V; I
D
= 3.3 mA
drain-source on-state resistance V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 11.55 A
Table 7.
RF characteristics
Test signal: 2-carrier W-CDMA; PAR = 7.5 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 64 DPCH; f
1
= 920 MHz; f
2
= 925 MHz; f
3
= 955 MHz; f
4
= 960 MHz;
RF performance at V
DS
= 30 V; I
Dq
= 1800 mA; T
case
= 25
C; unless otherwise specified; in a
class-AB production test circuit.
Symbol
G
p
RL
in
D
ACPR
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
Conditions
P
L(AV)
= 60 W
P
L(AV)
= 60 W
P
L(AV)
= 60 W
P
L(AV)
= 60 W
Min
18.5
-
27
-
Typ
19.5
15.5
30.5
34
Max
-
10
-
31
Unit
dB
dB
%
dBc
7. Test information
7.1 Ruggedness in class-AB operation
The BLF7G10L-250 and BLF7G10LS-250 are capable of withstanding a load mismatch
corresponding to VSWR = 10 : 1 through all phases under the following conditions:
V
DS
= 30 V; I
Dq
= 1800 mA; P
L
= 200 W (CW); f = 920 MHz to 960 MHz.
7.2 Impedance information
Table 8.
Typical impedance information
I
Dq
= 1800 mA; main transistor V
DS
= 30 V.
Z
S
and Z
L
defined in
Figure 1.
f
(MHz)
925
942
960
Z
S
()
3.1
j3.3
3.2
j3.3
3.4
j3.5
Z
L
()
1.0
j1.7
1.0
j1.6
0.9
j1.4
BLF7G10L-250_7G10LS-250
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2016
3 of 13
BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 Circuit
C5
C7 C8
C2
C11 C12
C15
C1
C4
BLF7G10L(S)-250
C9 C10
C3
C6
C13 C14
C16
aaa-001570
Printed-Circuit Board (PCB): Rogers RO3006;
r
= 6.15 F/m; thickness = 0.635 mm; thickness copper plating = 35
m.
The vias can be used as a reference to place components.
The above layout shows the test circuit used to measure the devices in production. A more appropriate application
demonstration for specific customer needs can be provided.
See
Table 9
for list of components.
Fig 2.
Component layout
Table 9.
List of components
See
Figure 2
for component layout.
Component
C1, C2, C3, C4, C5, C6
C7, C9, C12, C14
C8, C10, C11, C13
C15, C16
Description
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
multilayer ceramic chip capacitor
electrolytic capacitor
Value
82 pF
10
F
1
F
470
F,
63 V
Remarks
ATC800B
Murata
Murata
BLF7G10L-250_7G10LS-250
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2016
4 of 13
BLF7G10L-250; BLF7G10LS-250
Power LDMOS transistor
7.4 Graphs
7.4.1 CW pulsed
aaa-001555
aaa-001556
22
G
p
(dB)
18
G
p
(1)
(2)
(3)
60
η
D
(%)
40
22
G
p
(dB)
18
G
p
(1)
(2)
(3)
(1)
(2)
(3)
60
η
D
(%)
40
(1)
(2)
(3)
η
D
14
20
14
η
D
20
10
44
48
52
P
L
(dBm)
56
0
10
0
120
240
P
L
(W)
0
360
V
DS
= 30 V; I
Dq
= 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
V
DS
= 30 V; I
Dq
= 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 3.
Power gain and drain efficiency as function of
output power; typical values
-12
RL
in
(dB)
-14
(1)
Fig 4.
Power gain and drain efficiency as function of
output power; typical values
aaa-001559
-16
(2)
(3)
-18
-20
44
48
52
P
L
(dBm)
56
V
DS
= 30 V; I
Dq
= 1800 mA.
(1) f = 920 MHz
(2) f = 940 MHz
(3) f = 960 MHz
Fig 5.
Input return loss as a function of output power; typical values
BLF7G10L-250_7G10LS-250
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2016. All rights reserved.
Product data sheet
Rev. 6 — 7 November 2016
5 of 13
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