AZ2015-04S
Transient Voltage Suppressing Array
For ESD/Transient Protection
Features
Circuit Diagram
ESD Protect for 4 Lines with Unidirectional.
Provide ESD protection for each line to
IEC 61000-4-2 (ESD) ±16kV (air), ±10kV (contact)
IEC 61000-4-4 (EFT) 20A (5/50ns)
IEC 61000-4-5 (Lightning) 6A (8/20μs)
1
3
4
5
Below 5V operating voltage
Fast turn-on and Low clamping voltage
Array of surge rated equivalent TVS diodes
Small package saves board space
Solid-state silicon-avalanche and active circuit
triggering technology
Applications
Cellular Handsets and Accessories
Small Panel Modules
PDA’s
Portable Devices
Digital Cameras
Touch Panels
Notebooks and Handhelds
MP3 Players
Peripherals
2
Pin Configuration
5
4
Description
AZ2015-04S is a design which includes surge
rated clamping cell arrays to protect the power
lines or data/control lines in an electronic
systems. The AZ2015-04S has been specifically
designed to protect sensitive components which
are connected to power and control lines from
over-voltage caused by Electrostatic Discharging
(ESD), Electrical Fast Transients (EFT), and
Lightning.
AZ2015-04S is a unique design which includes
proprietary clamping cells in a single package.
During transient conditions, the proprietary
clamping cells prevent over-voltage on the power
lines or control lines, protecting any downstream
components.
AZ2015-04S may be used to meet the ESD
immunity requirements of IEC 61000-4-2, Level 4
(±15kV air,
±8kV
contact discharge).
1
2
SOT23-5L (Top View)
3
Revision 2007/12/17
©2007 Amazing Micro.
1
www.amazingIC.com
AZ2015-04S
Transient Voltage Suppressing Array
For ESD/Transient Protection
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Peak Pulse Current (tp =8/20us)
Operating Supply Voltage (pin-1,-2 to pin-3)
pin-1,-3, -4, -5 to pin-2 ESD per IEC 61000-4-2 (Air)
pin-1,-3, -4, -5 to pin-2 ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
T
SOL
T
OP
T
STO
ELECTRICAL CHARACTERISTICS
PARAMETER
Reverse Stand-Off
Voltage
Reverse Leakage
Current
Reverse
Breakdown Voltage
Forward Voltage
Surge Clamping
Voltage
ESD Clamping
Voltage
ESD Dynamic
Turn-on
Resistance
Channel Input
Capacitance
SYMBOL
V
RWM
I
Leak
V
BV
V
F
V
CL-surge
V
clamp
R
dynamic
C
IN
CONDITIONS
pin-1,-3, -4, -5 to pin-2, T=25
o
C.
V
RWM
= 5V, T=25
o
C, pin-1,-3, -4, -5 to pin-2.
I
BV
= 1mA, T=25
o
C, pin-1,-3, -4, -5 to pin-2
I
F
= 15mA, T=25
o
C, pin-2 to pin-1,-3, -4, -5
I
PP
=5A, tp=8/20us, T=25
o
C, pin-1,-3, -4, -5
to pin-2.
IEC 61000-4-2 +6kV, T=25
o
C,
Contact mode, pin-1,-3, -4, -5 to pin-2.
IEC 61000-4-2 0~+6kV, T=25
o
C,
Contact mode, pin-1,-3, -4, -5 to pin-2.
V
R
= 0V, f = 1MHz, T=25
o
C, pin-1,-3, -4, -5
to pin-2.
6
0.6
0.8
6.2
8
0.17
13
15
MINI
TYP
MAX
5
2.5
9
1
UNITS
V
μA
V
V
V
V
Ω
pF
PARAMETER
I
PP
V
DC
V
ESD-1
RATING
6A
6
16
10
260 (10 sec.)
-55 to +85
-55 to +150
UNITS
A
V
kV
kV
o
o
o
C
C
C
Revision 2007/12/17
©2007 Amazing Micro.
2
www.amazingIC.com
AZ2015-04S
Transient Voltage Suppressing Array
For ESD/Transient Protection
Typical Characteristics
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Typical Variation of CIN vs. VIN
Input Capacitance (pF)
f = 1MHz, T=25 oC,
0
1
2
3
4
5
Input Voltage (V)
Transmission Line Pulsing (TLP) Current (A)
Transmission Line Pulsing (TLP) Measurement
18
16
V_pulse
Pulse from a
transmission line
100ns
TLP_I
Clamping Voltage vs. Peak Pulse Current
12
11
10
Clamping Voltage (V)
9
8
7
6
5
4
3
2
1
0
4.5
I/O pin to GND pin
Waveform
Parameters:
tr=8μs
td=20μs
14
12
10
8
6
4
2
0
0
+
TLP_V
-
DUT
I/O to GND
2
4
6
8
5.0
5.5
6.0
6.5
7.0
Transmission Line Pulsing (TLP) Voltage (V)
Peak pulse Current (A)
Forward Clamping Voltage vs. Peak Pulse Current
5
Forward Clamping Voltage (V)
4
3
2
1
I/O pin to GND pin
Waveform
Parameters:
tr=8μs
td=20μs
0
4.5
5.0
5.5
6.0
6.5
7.0
Peak pulse Current (A)
Revision 2007/12/17
©2007 Amazing Micro.
3
www.amazingIC.com
AZ2015-04S
Transient Voltage Suppressing Array
For ESD/Transient Protection
Applications Information
The AZ2015-04S is designed to protect four lines
against System ESD/EFT/Lightning pulses by
clamping them to an acceptable reference.
The usage of the AZ2015-04S is shown in Fig. 1.
Protected lines, such as data lines, control lines,
or power lines, are connected at pin 1, 3, 4, and 5.
The pin 2 should be connected directly to a
ground plane on the board. All path lengths
connected to the pins of AZ2015-04S should be
kept as short as possible to minimize parasitic
inductance in the board traces.
In order to obtain enough suppression of ESD
induced transient, good circuit board is critical.
Thus, the following guidelines are recommended:
Minimize the path length between the
protected lines and the AZ2015-04S.
Place the AZ2015-04S near the input
terminals or connectors to restrict transient
coupling.
The ESD current return path to ground
should be kept as short as possible.
Use ground planes whenever possible.
NEVER route critical signals near board
edges and near the lines which the ESD
transient easily injects to.
Fig. 2 shows an example of PCB layout with the
AZ2015-04S.
Connector
I/O 2
I/O 3
I/O 4
GND
5
4
1
2
3
Fig. 1
Fig. 2
Revision 2007/12/17
©2007 Amazing Micro.
4
www.amazingIC.com
To the protected IC
To Connector
IC to be protected
I/O 1
1
2
3
5
4
AZ2015-04S
Transient Voltage Suppressing Array
For ESD/Transient Protection
Mechanical Details
SOT23-5L
PACKAGE DIAGRAMS
TOP VIEW
PACKAGE DIMENSIONS
SIDE VIEW
END VIEW
Revision 2007/12/17
©2007 Amazing Micro.
5
www.amazingIC.com
MicroPython开源版块
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
