HFBR-5208xxxZ
1 x 9 Fiber Optic Transceivers for 622 Mb/s
ATM/SONET/SDH Applications
Data Sheet
Description
General
The HFBR-5208xxxZ (multimode transceiver) from Avago
allow the system designer to implement a range of solu-
tions for ATM/SONET STS-12/SDH STM-4 applications.
The overall Avago transceiver consists of three sections:
the transmitter and receiver optical subassemblies, an
electrical subassembly and the mezzanine package
housing which incorporates a duplex SC connector
receptacle.
Features
x
Links of 500 m with 62.5/125 μm multimode fiber
(MMF) from 155-622 Mb/s
x
RoHS compliant
x
Compliant with ATM forum 622.08 Mb/s physical layer
specification (AF-PHY-0046.000)
x
Compliant with ANSI broadband ISDN - physical layer
specification T1.646-1995 and T1.646a-1997
x
HFBR-5208xxxZ is compliant with ANSI network to
customer installation interfaces - synchronous optical
NETwork (SONET) physical media dependent specifi-
cation: multimode fiber T1.416.01-1998
x
Industry-standard multi-sourced 1 x 9 mezzanine
package style
x
Single +5 V power supply operation and PECL logic
interfaces
x
Wave solder and aqueous wash process compatible
Transmitter Section
The transmitter section of the HFBR-5208xxxZ consists
of a 1300 nm LED in an optical subassembly (OSA) which
mates to the multimode fiber cable. The OSA’s are driven
by a custom, silicon bipolar IC which converts differential
PECL logic signals (ECL referenced to a +5 V supply) into
an analog LED drive current.
Applications
x
General purpose low-cost MMF links at 155 to 650
Mb/s
x
ATM 622 Mb/s MMF links from switch-to-switch or
switch-to-server in the end-user premise
x
Private MMF interconnections at 622 Mb/s SONET
STS-12/SDH STM-4 rate
Receiver Section
The receiver contains an InGaAs PIN photodiode mounted
together with a custom, silicon bipolar transimpedance
preamplifier IC in an OSA. This OSA is mated to a custom,
silicon bipolar circuit providing post amplification and
quantization and optical signal detection.
The custom, silicon bipolar circuit includes a Signal Detect
circuit which provides a PECL logic high state output
upon detection of a usable input optical signal level. This
single-ended PECL output is designed to drive a standard
PECL input through normal 50 W PECL load.
Applications Information
Typical BER Performance of HFBR-5208xxxZ Receiver versus Input Optical Power Level
The HFBR-5208xxxZ transceiver can be operated at Bit-
Error-Ratio conditions other than the required BER = 1
x 10
-10
of the 622 MBd ATM Forum 622.08 Mb/s Physical
Layer Standard and the ANSI T1.646a. The typical trade-
off of BER versus Relative Input Optical Power is shown
in Figure 1. The Relative Input Optical Power in dB is
referenced to the Input Optical Power parameter value
in the Receiver Optical Characteristics table. For better
BER condition than 1 x 10
-10
, more input signal is needed
(+dB). For example, to operate the HFBR-5208xxxZ at a
BER of 1 x 10
-12
, the receiver will require an input signal
approximately 0.6 dB higher than the -26 dBm level re-
quired for 1 x 10
-10
operation, i.e. -25.4 dBm.
10
-2
10
-3
10
-4
BIT ERROR RATIO
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-14
10
-15
Relative Input Optical Power amount (dB) is referenced to
the absolute level (dBm avg.) given in the Receiver Optical
Characteristics table. The 0 ns sampling time position
for this Figure 2 refers to the center of the Baud interval
for the particular signaling rate. The Baud interval is the
reciprocal of the signaling rate in MBd. For example, at
622 MBd the Baud interval is 1.61 ns, at 155 MBd the Baud
interval is 6.45 ns. Test conditions for this tub diagram are
listed in Figure 2.
The HFBR-5208xxxZ receiver input optical power require-
ments vary slightly over the signaling rate range of 20
MBd to 700 MBd for a constant bit-error-ratio (BER) of
10
-10
condition. Figure 3 illustrates the typical receiver
relative input optical power varies by <0.7 dB over this
full range. This small sensitivity variation allows the
optical budget to remain nearly constant for designs that
make use of the broad signaling rate range of the HFBR-
5208xxxZ. The curve has been normalized to the input
optical power level (dBm avg.) of the receiver for 622 MBd
at center of the Baud interval with a BER of 10
-10
. The data
patterns that can be used at these signaling rates should
be, on average, balanced duty factor of 50%. Momentary
excursions of less or more data duty factor than 50% can
occur, but the overall data pattern must remain balanced.
Unbalanced data duty factor will cause excessive pulse-
width distortion, or worse, bit errors. The test conditions
are listed in Figure 3.
LINEAR EXTRAPOLATION OF
10
-4
THROUGH 10
-7
DATA
ACTUAL DATA
-5
-4
-3
-2
-1
0
1
2
3
Figure 1. Relative Input Optical Power - dBm Average.
Recommended Circuit Schematic
When designing the HFBR-5208xxxZ circuit interface, there
are a few fundamental guidelines to follow. For example, in
the Recommended Circuit Schematic, Figure 4, the differential
data lines should be treated as 50 ohm Microstrip or stripline
transmission lines. This will help to minimize the parasitic
inductance and capacitance effects. Proper termination of
the differential data signal will prevent reflections and ringing
which would compromise the signal fidelity and generate
unwanted electrical noise. Locate termination at the received
signal end of the transmission line. The length of these lines
should be kept short and of equal length to prevent pulse-
width distortion from occurring. For the high-speed signal
lines, differential signals should be used, not single-ended
signals. These differential signals need to be loaded symmetri-
cally to prevent unbalanced currents from flowing which will
cause distortion in the signal.
An informative graph of a typical, short fiber transceiver
link per-formance can be seen in Figure 2. This figure is
useful for designing short reach links with time-based
jitter requirements. This figure indicates Relative Input
Optical Power versus Sampling Time Position within the
receiver output data eye-opening. The given curves are
at a constant bit-error-ratio (BER) of 10
-10
for four differ-
ent signaling rates, 155 MBd, 311 MBd, 622 MBd and 650
MBd. These curves, called “tub” diagrams for their shape,
show the amount of data eye-opening time-width for
various receiver input optical power levels. A wider data
eye-opening provides more time for the clock recovery
circuit to operate within without creating errors. The
deeper the tub is indicates less input optical power is
needed to operate the receiver at the same BER condition.
Generally, the wider and deeper the tub is the better. The
2
3
Equivalent Average Optical Input Power in dBm for extrapolated BER =le -10
2.5
2
155.52 M B d
311.04 M B d
622.08 M B d
650.00 M B d
1.5
1
0.5
0
-0 .5
-1
-3.5
-2 .5
-1 .5
-0 .5
0.5
1.5
2.5
3.5
Clock to Data Offset Delay in nsec (0 = Data Eye Center)
Figure 2. HFBR-5208xxMZ Relative Input Optical Power as a function of sampling time position. Normalized to center of Baud interval at 622 MBd. Test
Conditions +25°C, 5.25 V, PRBS 2
23
-1, optical
W
r
/W
f
= 0.9 ns with 3 m of 62.5 μm MMF.
2.5
HFBR-5208xxMZ
2
Relative Sensitivity in dB for extrapolated BER = le -10
1.5
1
0.5
0
-0.5
-1
-1.5
20
105
190
275
360
445
530
615
700
Module Data Stream Serial Data Rate in MBd
Figure 3. Relative Input Optical Power as a function of data rate normalized to center of Baud interval at 622 MBd.
Test Conditions +25°C, 5.25 V, PRBS 2
23
-1, optical
W
r
/W
f
= 0.9 ns with 3 m of MMF or SMF.
3
Maintain a solid, low inductance ground plane for returning
signal currents to the power supply. Multilayer plane printed
circuit board is best for distribution of V
CC
, returning ground
currents, forming transmission lines and shielding. Also, it
is important to suppress noise from influencing the fiber-
optic transceiver per-formance, especially the receiver
circuit. Proper power supply filtering of V
CC
for this trans-
ceiver is accomplished by using the recommended sepa-
rate filter circuits shown in Figure 4. These filter circuits
suppress V
CC
noise of 100 mV peak-to-peak or less over
a broad frequency range. This prevents receiver sensitiv-
ity degradation . It is recommended that surface-mount
components be used. Use tantalum capacitors for the 10
μF capacitors and monolithic, ceramic bypass capacitors
for the 0.1 μF capacitors. Also, it is recommended that a
surface-mount coil inductor of 1 μH be used. Ferrite beads
can be used to replace the coil inductors when using
quieter V
CC
supplies, but a coil inductor is recommended
over a ferrite bead to provide low-frequency noise filtering
as well. Coils with a low, series dc resistance (<0.7 ohms)
and high, self-resonating frequency are recommended. All
power supply components need to be placed physically
next to the V
CC
pins of the receiver and transmitter. Use a
good, uniform ground plane with a minimum number of
holes to provide a low-inductance ground current return
path for the signal and power supply currents.
Although the front mounting posts make contact with the
metallized housing, these posts should not be relied upon to
provide adequate electrical connection to the plated housing.
It is recommended to either connect these front posts to
chassis ground or allow them to remain unconnected. These
front posts should not be connected to signal ground.
Figure 5 shows the recommended board layout pattern.
In addition to these recommendations, Avago Technologies
Application Engineering staff is available for consulting
on best layout practices with various vendors’ serializer/
deserializer, clock recovery/generation integrated circuits.
MOUNTING POST
NO INTERNAL CONNECTION
MOUNTING POST
NO INTERNAL CONNECTION
HFBR-5208xxxZ
TOP VIEW
Rx
V
EER
1
RD
2
RD
3
SD
4
Rx
V
CCR
5
Tx
V
CCT
6
TD
7
TD
8
Tx
V
EET
9
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS
NEED TO BE LOCATED AT THE INPUT OF DEVICES
RECEIVING THOSE PECL SIGNALS. RECOMMEND
MULTI-LAYER PRINTED CIRCUIT BOARD WITH 50 OHM
MICROSTRIP OR STRIPLINE SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 F.
C4 = C7 = 10 F.
L1 = L2 = 1 H COIL OR FERRITE INDUCTOR
(see text comments).
C1
C2
V
CC
TERMINATION
AT PHY
DEVICE
INPUTS
C7
V
CC
R5
C6
R7
L1
L2
R2
R1
R3
R4
C5
R6
R8
C3
C4
V
CC
FILTER
AT V
CC
PINS
TRANSCEIVER
R9
R10
TERMINATION
AT TRANSCEIVER
INPUTS
RD
RD
SD
V
CC
TD
TD
Figure 4. Recommended Circuit Schematic for dc Coupling (at +5 V) between Optical Transceiver and Physical Layer IC
4
Reference Design
Avago has developed a reference design for multimode
ATM-SONET/SDH applications shown in Figure 6. This ref-
erence design uses a Vitesse Semiconductor Inc.’s VSC8117
clock recovery/clock generation/serializer/deserializer
integrated circuit and a PMC-Sierra Inc. PM5355 framer
IC. Application Note 1178 documents the design, layout,
testing and performance of this reference design. Gerber
files, schematic and application note are available from
the Avago Fiber-Optics Components’ web site at the URL
of
http://www.avagotech.com.
Operation in -5.2 V Designs
For applications that require -5.2 V dc power supply level
for true ECL logic circuits, the HFBR-5208xxxZ transceiver
can be operated with a V
CC
= 0 V dc and a V
EE
= -5.2 V dc.
This transceiver is not specified with an operating, nega-
tive power supply voltage. The potential compromises
that can occur with use of -5.2 V dc power are that the
absolute voltage states for V
OH
and V
OL
will be changed
slightly due to the 0.2 V difference in supply levels. Also,
noise immunity may be compromised for the HFBR-
5208xxxZ trans-ceiver because the ground plane is now
the V
CC
supply point. The suggested power supply filter
circuit shown in the Recommended Circuit Schematic
figure should be located in the V
EE
paths at the transceiver
supply pins. Direct coupling of the differential data signal
can be done between the HFBR-5208xxxZ transceiver
and the standard ECL circuits. For guaranteed -5.2 V dc
operation, contact your local Avago Component Field
Sales Engineer for assistance.
20.32
(0.800)
2 x Ø 1.9 ± 0.1
(0.075 ± 0.004)
20.32
(0.800)
9 x Ø 0.8 ± 0.1
(0.032 ± 0.004)
2.54
(0.100)
TOP VIEW
DIM EN S IO N S A RE IN M ILLIM ETERS (IN C HES )
Figure 5. Recommended Board Layout Pattern
Figure 6. 622.08 Mb/s OC-12 ATM-SONET/SDH Reference Design Board
5
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