HFBR-5963LZ/ALZ
Multimode Small Form Factor Transceivers for ATM, FDDI,
Fast Ethernet and SONET OC-3/SDH STM-1 with LC Connector
Data Sheet
Description
The HFBR-5963xxZ transceiver provides the system
designer with a product to implement a range of solutions
for multimode fiber Fast Ethernet and SONET OC-3 (SDH
STM-1) physical layers for ATM and other services.
This transceiver is supplied in the industry standard 2 x
5 DIP style with an LC fiber connector interface with an
external connector shield.
Features
RoHS compliant
Multisourced 2 x 5 package style
Operates with 62.5/125 mm and 50/125 mm multi-
mode fiber
Single +3.3 V power supply
Wave solder and aqueous wash process compatibility
Manufactured in an ISO 9001 certified facility
Full compliance with ATM Forum
UNI SONET OC-3 multimode fiber physical layer speci-
fication
Applications
SONET/SDH equipment interconnect, OC-3/SDH
STM-1 rate
Fast Ethernet
Multimode fiber ATM backbone links
Full compliance with the optical performance require-
ments of the FDDI PMD standard
Full compliance with the optical performance require-
ments of 100Base-FX version of IEEE802.3u
+3.3 V TTL signal detect output
Temperature range:
0 °C to +70 °C
-40 °C to +85 °C
HFBR-5963LZ
HFBR-5963ALZ
Transmitter Section
The transmitter section of the HFBR-5963xxZ utilizes a
1300 nm InGaAsP LED. This LED is packaged in the optical
subassembly portion of the transmitter section. It is
driven by a custom silicon IC which converts differential
PECL logic signals, ECL referenced (shifted) to a +3.3 V
supply, into an analog LED drive current.
Package
The overall package concept for the Avago transceiver
consists of three basic elements; the two optical subas-
semblies, an electrical subassembly, and the housing as
illustrated in the block diagram in Figure 1.
The package outline drawing and pin out are shown in
Figures 2 and 5. The details of this package outline and
pin out are compliant with the multisource definition of
the 2 x 5 DIP. The low profile of the Avago transceiver
design complies with the maximum height allowed for
the LC connector over the entire length of the package.
The optical subassemblies utilize a high-volume assembly
process together with low-cost lens elements which result
in a cost- effective building block.
The electrical subassembly consists of a high volume mul-
tilayer printed circuit board on which the ICs and various
surface-mounted passive circuit elements are attached.
The receiver section includes an internal shield for the elec-
trical and optical subassemblies to ensure high immunity
to external EMI fields.
The outer housing including the LC ports is molded of filled
nonconductive plastic to provide mechanical strength.
The solder posts of the Avago design are isolated from the
internal circuit of the transceiver.
The transceiver is attached to a printed circuit board
with the ten signal pins and the two solder posts which
exit the bottom of the housing. The two solder posts
provide the primary mechanical strength to withstand the
loads imposed on the transceiver by mating with the LC
connector fiber cables.
R
X
SUPPLY
Receiver Section
The receiver section of the HFBR-5963xxZ utilizes an
InGaAs PIN photodiode coupled to a custom silicon tran-
simpedance preamplifier IC. It is packaged in the optical
subassembly portion of the receiver.
This PIN/preamplifier combination is coupled to a custom
quantizer IC which provides the final pulse shaping for
the logic output and the signal detect function. The data
output is differential. The data output is PECL compat-
ible, ECL referenced (shifted) to a +3.3 V power supply.
The receiver outputs, data output and data out bar, are
squelched at signal detect deassert. The signal detect
output is single ended. The signal detect circuit works by
sensing the level of the received signal and comparing
this level to a reference. The SD output is +3.3 V TTL.
DATA OUT
DATA OUT
SIGNAL
DETECT
DATA IN
DATA IN
LED DRIVER IC
QUANTIZER IC
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
R
X
GROUND
T
X
GROUND
LC
RECEPTACLE
LED
OPTICAL
SUBASSEMBLY
T
X
SUPPLY
Figure 1. Block Diagram
2
Pin Descriptions:
Pin 1 Receiver Signal Ground V
EE
RX
Directly connect this pin to the receiver ground plane.
RX
TX
Pin 2 Receiver Power Supply Vcc RX
Provide +3.3 V dc via the recommended receiver power
supply filter circuit. Locate the power supply filter circuit
as close as possible to the V
CC
RX pin.
Mounting
Studs/Solder
Posts
Top
View
Pin 3 Signal Detect SD
Normal optical input levels to the receiver result in a logic
“1” output.
Low optical input levels to the receiver result in a logic “0”
output.
This Signal Detect output can be used to drive a +3.3 V TTL
input on an upstream circuit, such as Signal Detect input
or Loss of Signal-bar.
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
o
o
o
o
o
1
2
3
4
5
10
9
8
7
6
o
o
o
o
o
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
NC
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Pin 4 Receiver Data Out Bar RD-
No internal terminations are provided. See recommend-
ed circuit schematic.
Figure 2. Pin Out Diagram
Pin 5 Receiver Data Out RD+
No internal terminations are provided. See recommend-
ed circuit schematic.
Application Information
The Applications Engineering group is available to assist
you with the technical understanding and design trade-
offs associated with these transceivers. You can contact
them through your Avago sales representative.
The following information is provided to answer some
of the most common questions about the use of these
parts.
Pin 6 Transmitter Power Supply V
CC
TX
Provide +3.3 V dc via the recommended transmitter power
supply filter circuit.
Locate the power supply filter circuit as close as possible
to the V
CC
TX pin.
Pin 7 Transmitter Signal Ground V
EE
TX
Directly connect this pin to the transmitter ground plane.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available optical power
for a fiber optic link to accommodate fiber cable losses plus
losses due to in-line connectors, splices, optical switches,
and to provide margin for link aging and unplanned losses
due to cable plant reconfiguration or repair.
Avago LED technology has produced 1300 nm LED
devices with lower aging characteristics than normally
associated with these technologies in the industry. The
industry convention is 1.5 dB aging for 1300 nm LEDs. The
1300 nm Avago LEDs are specified to experience less than
1 dB of aging over normal commercial equipment mission
life periods.
Contact your Avago sales representative for additional
details.
Pin 8 NC
No connection.
Pin 9 Transmitter Data In TD+
No internal terminations are provided. See recommend-
ed circuit schematic.
Pin 10 Transmitter Data In Bar TD-
No internal terminations are provided. See recommend-
ed circuit schematic.
Mounting Studs/Solder Posts
The mounting studs are provided for transceiver mechani-
cal attachment to the circuit board.
It is recommended that the holes in the circuit board be
connected to chassis ground.
3
Recommended Handling Precautions
Avago recommends that normal static precautions be
taken in the handling and assembly of these transceivers
to prevent damage which may be induced by electrostatic
discharge (ESD).
The HFBR-5963xxZ series of transceivers meet MIL-STD-
883C Method 3015.4 Class 2 products.
Care should be used to avoid shorting the receiver data or
signal detect outputs directly to ground without proper
current limiting impedance.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD damage
during shipment or storage.
Board Layout - Decoupling Circuit, Ground Planes and
Termination Circuits
It is important to take care in the layout of your circuit
board to achieve optimum performance from these trans-
ceivers. Figure 3 provides a good example of a schematic
for a power supply decoupling circuit that works well
with these parts. It is further recommended that a con-
tiguous ground plane be provided in the circuit board
directly under the transceiver to provide a low inductance
ground for signal return current. This recommendation
is in keeping with good high frequency board layout
practices. Figures 3 and 4 show two recommended ter-
mination schemes.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
PHY DEVICE
V CC (+3.3 V)
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50
Ω
TD-
100
Ω
Z = 50
Ω
LVPECL
TD+
130
Ω
130
Ω
10 9 8 7 6
TD- o
V EET X o
TD+ o
V CC T X o
1 μH
C2
V CC (+3.3 V)
C3
10 μF
V CC (+3.3 V)
TX
o V EER X
o V CC R X
o RD+
RX
N/C
o
o SD
o RD-
1 μH
RD+
C1
Z = 50
Ω
100
Ω
RD-
Z = 50
Ω
V CC (+3.3 V)
R1*
Z = 50
Ω
4.7KΩ
SD
LVPECL
1 2 3 4 5
130
Ω
130
Ω
LVTTL
Notes:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading of R1 is optional.
TERMINATE AT
DEVICE INPUTS
Figure 3. Recommended Decoupling and Termination Circuits
4
Board Layout - Hole Pattern
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint” hole pattern defined in
the original multisource announcement which defined the
2 x 5 package style. This drawing is reproduced in Figure
6 with the addition of ANSI Y14.5M compliant dimension-
ing to be used as a guide in the mechanical layout of your
circuit board. Figure 6 illustrates the recommended panel
opening and the position of the circuit board with respect
to this panel.
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certification of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago sales representative.
TERMINATE AT
TRANSCEIVER INPUTS
V CC (+3.3 V)
PHY DEVICE
V CC (+3.3 V)
10 nF
130
Ω
130
Ω
Z = 50
Ω
TD-
Z = 50
Ω
LVPECL
TD+
10 9 8 7
6
82
Ω
82
Ω
V CC (+3.3 V)
V CC T X o
V EET X o
TD+ o
TD- o
N/C
o
TX
1 μH
C2
V CC (+3.3 V)
C3
10 μF
10 nF
130
Ω
130
Ω
RD+
V CC (+3.3 V)
o V EER X
o V CC R X
o RD-
o SD
o RD+
RX
1 μH
C1
1 2 3 4 5
Z = 50
Ω
V CC (+3.3 V)
R1*
Z = 50
Ω
4.7KΩ
82
Ω
82
Ω
SD
LVPECL
RD-
Z = 50
Ω
LVTTL
Note:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading R1 is optional.
TERMINATE AT DEVICE INPUTS
Figure 4. Alternative Termination Circuits
5
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