AFBR-810BxxxZ and AFBR-820BxxxZ
Twelve-Channel Transmitter and Receiver
Pluggable, Parallel-Fiber-Optic Modules
Data Sheet
Description
The AFBR-810B Twelve-Channel, Pluggable, Parallel-Fiber-
Optic Transmitter and AFBR-820B Twelve-Channel,
Pluggable, Parallel-Fiber-Optic Receiver are high per-
formance fiber Optic modules for short-range parallel
multi-lane data communication and interconnect ap-
plications. These 12-channel devices are capable of 10.0
Gbps per channel, 120 Gbps raw aggregate operation.
The modules are designed to operate over multimode
fiber systems using a nominal wavelength of 850 nm. The
electrical interface uses a 10x10 MEG-Array
low-profile
mezzanine connector. The optical interface uses a MTP
(MPO) 1x12 ribbon cable connector. The thermal interface
can be a factory installed heatsink for air-cooled systems
or thermal seating plane for user flexibility. The modules
incorporate high performance, highly reliable, short
wavelength optical devices coupled with proven circuit
technology to provide long life and consistent service.
Features
•
High Channel Capacity: 120 Gbps per module
•
High port density: 19 mm lateral port pitch; < 0.51 mm/
Gbps for Tx–Rx pair
•
Low power consumption per Gbps: < 42 mW/Gb/s for
Tx–Rx pair
•
Based on industry-standard, pluggable, SNAP12 form
factor with upgraded pinout for improved signal
integrity and keyed to prevent mis-plugging with first
generation SNAP12 devices
•
Twelve independent channels per module
•
Separate transmitter and receiver modules
•
850 nm VCSEL array in transmitter; PIN array in receiver
•
Operates up to 10 Gbps with 8b/10b compatible coded
data
•
Links up to 50 m at 10 Gbps with 2000 MHz∙km 50 um
MMF
•
Two power supplies, 2.5 V and 3.3 V, for low power
consumption
•
Dedicated signals for module address, module reset
and host interrupt.
•
Two Wire Serial (TWS) interface with maskable interrupt
for expanded functionality including:
– Individual channel functions: disable, squelch
disable, lane polarity inversion, margin
– Programmable equalization integrated with DC
blocking caps at transmitter data input
– Programmable receiver output swing and de-
emphasis level
– A/D readback: module temperature and supply
voltages, per channel laser current and laser power,
or received power
– Status: per channel Tx fault, electrical (transmitter)
or optical (receiver) LOS, and alarm flags
•
0 to 70°C case temperature operating range
Applications
•
High Performance and High Productivity computer
interconnects
•
InfiniBand QDR SX interconnects
•
Datacom switch and router backplane connections
•
Telecom switch and router backplane connections
Part Number Ordering Options
Transmitter Part Numbers
AFBR-810BZ
AFBR-810BEZ
AFBR-810BPZ
AFBR-810BEPZ
AFBR-810BHZ
AFBR-810BEHZ
AFBR-820BZ
AFBR-820BEZ
AFBR-820BPZ
AFBR-820BEPZ
AFBR-820BHZ
AFBR-820BEHZ
With Fin heat sink / no EMI nose clip
With Fin heat sink / EMI nose clip
With Pin heat sink / no EMI nose clip
With Pin heat sink / EMI nose clip
With no heat sink / no EMI nose clip
With no heat sink/ EMI nose clip
With Fin heat sink / no EMI nose clip
With Fin heat sink / EMI nose clip
With Pin heat sink / no EMI nose clip
With Pin heat sink / EMI nose clip
With no heat sink / no EMI nose clip
With no heat sink/ EMI nose clip
Receiver Part Numbers
Patent -
www.avagotech.com/patents
Transmitter Module
The optical transmitter module (see Figure 1) incorporates
a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser)
array, a 12-channel input buffer and laser driver, diagnos-
tic monitors, control and bias blocks. The transmitter is
designed for IEC-60825 and CDRH eye safety compliance;
Class 1M out of the module. The Tx Input Buffer provides
CML compatible differential inputs (presenting a nominal
differential input impedance of 100 Ohms and a nominal
common mode impedance to signal ground of 25 Ohms)
for the high speed electrical interface that can operate
over a wide common mode range without requiring DC
blocking capacitors. For module control and interroga-
tion, the control interface (LVTTL compatible) incorpo-
rates a Two Wire Serial (TWS) interface of clock and data
signals and dedicated signals for host interrupt, module
address setting and module reset. Diagnostic monitors for
VCSEL bias, light output (LOP), temperature, both supply
voltages and elapsed operating time are implemented
and results are available through the TWS interface.
Over the TWS interface, the user can, for individual
channels, control (flip) polarity of the differential inputs,
de-activate channels, place channels into margin mode,
disable the squelch function and program input equaliza-
tion levels to reduce the effect of long PCB traces. A reset
for the control registers is available. Serial ID information
and alarm thresholds are provided. To reduce the need for
polling, the TWS interface is augmented with an interrupt
signal for the host.
Alarm thresholds are established for the monitored
attributes. Flags are set and interrupts generated when
the attributes are outside the thresholds. Flags are also set
and interrupts generated for loss of input signal (LOS) and
transmitter fault conditions. All flags are latched and will
remain set even if the condition initiating the latch clears
and operation resumes. All interrupts can be masked and
flags are reset by reading the appropriate flag register. The
optical output will squelch for loss of input signal unless
squelch is disabled. Fault detection or channel deactiva-
tion through the TWS interface will disable the channel.
Status, alarm and fault information are available via the
TWS interface. The interrupt signal (selectable via the TWS
interface as a pulse or static level) is provided to inform
hosts of an assertion of an alarm, LOS and/or Tx fault.
1 x 12 VCSEL Array
Din[11:0][p/n] (24)
SCL
SDA
IntL
Adr[2:0] (3)
ResetL
Vcc33 (4)
Vcc25 (2)
Gnd
Tx Input Buffer
12 Channels
Laser Driver
12 Channels
Electrical Interface
Control
Diagnostic Monitors
Bias
Figure 1. Transmitter Block Diagram
2
Optical Interface
Receiver Module
The optical receiver module (see Figure 2) incorporates
a 12-channel PIN photodiode array, a 12-channel pre-
amplifier and output buffer, diagnostic monitors, control
and bias blocks. The Rx Output Buffer provides CML
compatible differential outputs for the high speed elec-
trical interface presenting nominal single-ended output
impedances of 50 Ohms to AC ground and 100 Ohms
differentially that should be differentially terminated with
100 Ohms. DC blocking capacitors may be required. For
module control and interrogation, the control interface
(LVTTL compatible) incorporates a Two Wire Serial (TWS)
interface of clock and data signals and dedicated signals
for host interrupt, module address setting and module
reset. Diagnostic monitors for optical input power, tem-
perature, both supply voltages and elapsed operating
time are implemented and results are available through
the TWS interface.
Over the TWS interface, the user can, for individual
channels, control (flip) polarity of the differential outputs,
de-activate channels, disable the squelch function,
program output signal amplitude and de-emphasis
and change receiver bandwidth. A reset for the control
registers is available. Serial ID information and alarm
thresholds are provided. To reduce the need for polling,
the TWS interface is augmented with an interrupt signal
for the host.
Alarm thresholds are established for the monitored at-
tributes. Flags are set and interrupts generated when the
attributes are outside the thresholds. Flags are also set
and interrupts generated for loss of optical input signal
(LOS). All flags are latched and will remain set even if
the condition initiating the latch clears and operation
resumes. All interrupts can be masked and flags are reset
upon reading the appropriate flag register. The electri-
cal output will squelch for loss of input signal (unless
squelch is disabled) and channel de-activation through
TWS interface. Status and alarm information are available
via the TWS interface. The interrupt signal (selectable via
the TWS interface as a pulse or static level) is provided
to inform hosts of an assertion of an alarm and/or LOS.
Dout[11:0][p/n] (24) Rx Output Buffer
12 Channels
Electrical Interface
SCL
SDA
IntL
Adr[2:0] (3)
ResetL
Vcc33 (4)
Vcc25 (2)
Gnd
Preamp
12 Channels
Control
Diagnostic Monitors
Bias
Figure 2. Receiver Block Diagram
3
Optical Interface
1 x 12 PIN Array
High Speed Signal Interface
Figure 3 shows the interface between an ASIC/SerDes and
the fiber Optic modules. For simplicity, only one channel is
shown. As shown in the Figure 3, the compliance points are
on the host board side of the electrical connectors.Sets of
s-parameters are defined for the transmitter and receiver
interfaces. The transmitter and receiver are designed,
when operating within Recommended Operating Con-
ditions, to provide a robust eye-opening at the receiver
outputs. See the Recommended Operating Conditions
and the Receiver Electrical Characteristics for details.
Unused inputs and outputs should be terminated with
100
Ω
differential loads.
The transmitter inputs support a wide common mode
range and DC blocking capacitors may not be needed –
none are shown in Figure 3. Depending on the common
mode range tolerance of the ASIC/SerDes inputs, DC
blocking capacitors may be required in series with the
receiver. Differential impedances are nominally 100
Ω.
The common mode output impedance for the receiver is
nominally 25
Ω
while the nominal common mode input
impedance of the transmitter is 25
Ω.
Transmitter Input Equalization
Transmitter inputs can be programmed for one of several
levels of equalization. See Figure 4. Different levels of
compensation can be selected to equalize skin-effect
losses across the host circuit board. See Tx Memory Map
01h Upper Page section addresses 228 - 233 for program-
ming details.
No Equalization
Gain
Maximum Equalization
Frequency
Figure 4. Input Equalization
FO Rx Electrical Interface
ASIC/SerDes
CAC
100
Ω
SDD22
SCC22
SDC22
50
Ω
50
Ω
FO Rx (1 of 12 Lanes)
CAC
Host Board Electrical Interface
- Compliance Points -
50
Ω
50
Ω
SDD11
SCC11
SCD11
Figure 3. Application Reference Diagram
4
100
Ω
FO Tx (1 of 12 Lanes)
FO Tx Electrical Interface
Receiver Output Amplitude and De-emphasis
Receiver outputs can be programmed to provide several
levels of amplitude and de-emphasis. See Figure 5 for
de-emphasis definition. The user can program for peak-
to-peak amplitude and then a de-emphasis level. If zero
de-emphasis is selected, then the signal steady state equals
the peak-to-peak level. For other levels of de-emphasis the
selected de-emphasis reduces the steady-state from the
peak-to-peak level. The change from peak-to-peak level to
steady-state occurs within a bit time. See Rx Memory Map
01h Upper Page section addresses 228 - 233 for amplitude
programming details and addresses 234 – 239 for
de-emphasis programming details.
For optimal performance at
10 Gb/s, lowering the De-Emphasis setting below the default value of 4
is not recommended.
Data
0
1
0
0
0
1
0
1
1 bit
1
1
Package Outline
The module is designed to meet the package outline
defined in the PPOD MSA. This MSA follows the outline
of the SNAP12 MSA except for the position of the MEG-
Array connector and pin assignments. See the package
outline and host board footprint figures (Figures 23 -26)
for details.
De-Emphasis (DE)
Output
Voltage
Steady-State (SS)
De-Emphasis % = (DE/SS)(100%)
Figure 5. Definition of De-emphasis and Steady State
Control Signal Interface
The control interface includes dedicated signals for
address inputs, interrupt output and reset input and bidi-
rectional clock and data lines for a two-wire serial access
(TWS interface) to control and status and information
registers. The TWS interface is compatible with industry
standard two-wire serial protocol scaled for 3.3 volt LVTTL.
It is implemented as a slave device. Signal and timing
characteristics are further defined in the Control Charac-
teristics and Control Interface & Memory Map sections.
The registers of the serial interface memory are defined in
the Control Interface & Memory Map section.
Handling and Cleaning
The transmitter and receiver modules can be damaged
by exposure to current surges and over voltage events.
Care should be taken to restrict exposure to the condi-
tions defined in the Absolute Maximum Ratings. Wave
soldering, reflow soldering and/or aqueous wash process
with the modules on board are not recommended. Normal
handling precautions for electrostatic discharge sensitive
devices should be observed.
Each module is supplied with an inserted port plug for
protection of the optical ports. This plug should always be
in place whenever a fiber cable is not inserted.
The optical connector includes recessed elements that
are exposed whenever a cable or port plug is not inserted.
Prior to insertion of a fiber optic cable, it is recommended
that the cable end be cleaned to avoid contamination
from the cable plug. The port plug ensures the Optic
remain clean and no addition cleaning should be needed.
In the event of contamination, dry nitrogen or clean dry
air at less than 20 psi can be used to dislodge the contami-
nation. The optical port features (e.g. guide pins) preclude
use of a solid instrument. Liquids are also not advised.
Regulatory & Compliance Issues
Various standard and regulations apply to the modules.
These include eye-safety, EMC, ESD and RoHS. See the Reg-
ulatory Section for details regarding these and component
recognition. Please note the transmitter module is a Class
1M laser product – DO NOT VIEW RADIATION DIRECTLY
WITH OPTICAL INSTRUMENTS. See Regulatory Compliance
Table for details. When released, the AFBR- will support
this table.
5
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
