ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V
Speed
- Read max frequency : 33MHz
- Fast Read max frequency : 50MHz; 75MHz; 100MHz
Low power consumption
- Active current：40mA
- Standby current：75
μ
A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte program time 9
μ
s(typical)
Erase
- Chip erase time 4s(typical)
- Block erase time 1sec (typical)
- Sector erase time 90ms(typical)
F25L004A
Operation Temperature Condition -40
°C
~85
°C
3V Only 4 Mbit Serial Flash Memory
Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte-Program operations
SPI Serial Interface
- SPI Compatible : Mode 0 and Mode3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Part No.
F25L004A –50PIG
F25L004A –100PIG
F25L004A –50PAIG
Speed
50MHz
100MHz
50MHz
Package
8 lead
SOIC
8 lead
SOIC
8 lead
SOIC
150 mil
150 mil
200 mil
COMMENTS
Pb-free
Pb-free
Pb-free
Part No.
Speed
Package
8 lead
SOIC
8 lead
PDIP
8 lead
PDIP
200 mil
300 mil
300 mil
COMMENTS
Pb-free
Pb-free
Pb-free
F25L004A –100PAIG 100MHz
F25L004A –50DIG
F25L004A –100DIG
50MHz
100MHz
GENERAL DESCRIPTION
The F25L004A is a 4Megabit, 3V only CMOS Serial Flash
memory device. ESMT’s memory devices reliably store memory
data even after 100,000 program and erase cycles.
The F25L004A features a sector erase architecture. The device
memory array is divided into 128 uniform sectors with 4K byte
each ; 8 uniform blocks with 64K byte each. Sectors can be
erased individually without affecting the data in other sectors.
Blocks can be erased individually without affecting the data in
other blocks. Whole chip erase capabilities provide the flexibility
to revise the data in the device.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision:
1.3
1/33
ESMT
PIN CONFIGURATIONS
8-PIN SOIC
F25L004A
Operation Temperature Condition -40
°C
~85
°C
CE
1
8
VDD
SO
2
3
7
6
HOLD
SCK
WP
VSS
4
5
SI
8-PIN PDIP
CE
1
8
VDD
SO
2
3
7
6
HOLD
SCK
WP
VSS
4
5
SI
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision:
1.3
2/33
ESMT
PIN Description
Symbol
SCK
SI
Pin Name
Serial Clock
Serial Data Input
Functions
To provide the timing for serial input and
output operations
To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to
enable/disable BPL bit in the status
register.
To temporality stop serial communication
with SPI flash memory without resetting
the device.
To provide power.
F25L004A
Operation Temperature Condition -40
°C
~85
°C
SO
CE
WP
Serial Data Output
Chip Enable
Write Protect
HOLD
VDD
VSS
Hold
Power Supply
Ground
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision:
1.3
3/33
ESMT
SECTOR STRUCTURE
F25L004A
Operation Temperature Condition -40
°C
~85
°C
Table1 : F25L004A Sector Address Table
Block
7
Sector
127
:
112
111
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
07F000H – 07FFFFH
:
070000H – 070FFFH
06F000H – 06FFFFH
:
060000H – 060FFFH
05F000H – 05FFFFH
:
050000H – 050FFFH
04F000H – 04FFFFH
:
040000H – 040FFFH
03F000H – 03FFFFH
:
030000H – 030FFFH
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
Block Address
A18 A17 A16
1
1
1
6
:
96
95
1
1
0
5
:
80
79
1
0
1
4
:
64
63
1
0
0
3
:
48
47
0
1
1
2
:
32
31
0
1
0
1
:
16
15
0
0
1
0
:
0
0
0
0
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision:
1.3
4/33
ESMT
Table2 : F25L004A Block Protection Table
F25L004A
Operation Temperature Condition -40
°C
~85
°C
Protection Level
0
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
All Blocks
0
0
0
0
1
1
1
1
Status Register Bit
BP2
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
Protected Memory Area
Block Range
None
Block 7
Block 6~7
Block 4~7
Block 0~7
Block 0~7
Block 0~7
Block 0~7
Address Range
None
70000H – 7FFFFH
60000H – 7FFFFH
40000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
00000H – 7FFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table2 to be software protected
against any memory Write (Program or Erase) operations. The
Write-Status-Register (WRSR) instruction is used to program the
BP2, BP1, BP0 bits as long as
WP
is high or the
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be
executed if Block-Protection bits are all 0. After power-up, BP2,
BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP
pin driven low (V
IL
), enables the Block-Protection
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP
pin is driven high (V
IH
), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision:
1.3
5/33
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