ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V
Standard, Dual SPI
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 100MHz
(100MHz / 200MHz equivalent Dual SPI)
Low power consumption
- Active current: 35 mA
- Standby current: 30
μ
A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte programming time: 7
μ
s (typical)
- Page programming time: 1.5 ms (typical)
Erase
- Chip erase time 10 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
Page Programming
- 256 byte per programmable page
F25L08PA
3V Only 8 Mbit Serial Flash Memory with Dual
Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte Program operations
Lockable 4K bytes OTP security sector
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25L08PA –50PG
F25L08PA –100PG
F25L08PA –50PAG
F25L08PA –100PAG
F25L08PA –50DG
F25L08PA –100DG
Speed
50MHz
100MHz
50MHz
100MHz
50MHz
100MHz
Package
8 lead SOIC
8 lead SOIC
8 lead SOIC
8 lead SOIC
8 lead PDIP
8 lead PDIP
150mil
150mil
200mil
200mil
300mil
300mil
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
GENERAL DESCRIPTION
The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 4,096 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction. The device also can be
programmed to decrease total chip programming time with Auto
Address Increment (AAI) programming.
The device features sector erase architecture. The memory array
is divided into 256 uniform sectors with 4K byte each; 16 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date:
Jul. 2009
Revision: 1.7
1/32
ESMT
PIN DESCRIPTION
Symbol
SCK
SI
Pin Name
Serial Clock
Serial Data Input
Functions
To provide the timing for serial input and
output operations
To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to
enable/disable BPL bit in the status
register.
To temporality stop serial communication
with SPI flash memory without resetting
the device.
To provide power.
F25L08PA
SO
CE
WP
Serial Data Output
Chip Enable
Write Protect
HOLD
VDD
VSS
Hold
Power Supply
Ground
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
and
Latches
X-Decoder
Flash
Y-Decoder
Control Logic
I/O Butters
and
Data Latches
Serial Interface
CE
SCK
SI
SO
WP
HOLD
Elite Semiconductor Memory Technology Inc.
Publication Date:
Jul. 2009
Revision: 1.7
3/32
ESMT
Table 1: F25L08PA Sector Address Table - Continued
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Block Address
A19 A18
0
0
A17
1
A16
0
Block
Sector
47
2
:
32
31
1
:
16
15
0
:
0
Address range
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
0
0
0
0
0
0
0
1
F25L08PA
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Bit
0
1
2
3
4
5
6
7
Note:
1. Only BP0, BP1, BP2 and BPL are writable.
2. All register bits are volatility
3. All area are protected at power-on (BP2=BP1=BP0=1)
Name
BUSY
WEL
BP0
BP1
BP2
RESERVED
AAI
BPL
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Reserved for future use
Auto Address Increment Programming status
1 = AAI programming mode
0 = Page Program mode
1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable
Default at
Power-up
0
0
1
1
1
0
0
0
Read/Write
R
R
R/W
R/W
R/W
N/A
R
R/W
Elite Semiconductor Memory Technology Inc.
Publication Date:
Jul. 2009
Revision: 1.7
5/32
FPGA/CPLD
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