NT1GD64S8HB0G / NT512D64S88B0G / NT256D64SH4B0G
NT1GD72S8PB0G / NT512D72S89B0G
1GB, 512MB, 256MB, 1GB(ECC) and 512MB(ECC)
PC3200 and PC2700
Unbuffered DDR DIMM
184 pin Unbuffered DDR DIMM
Based on DDR400/333 512M bit Die B device
Features
• 184 Dual In-Line Memory Module (DIMM)
• Unbuffered DDR DIMM based on 110nm 512M bit die B device
• ECC support in 1GB and 512MB modules
• Performance:
PC2700 PC3200
Speed Sort
DIMM
CAS
Latency
t
f
KC
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
Unit
MHz
ns
MHz
- DIMM
CAS
Latency: 2, 2.5 (6K); 2, 2.5 (5T)
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect EEPROM
• Gold contacts on module PCB
6K
2.5
166
6
333
5T
3
200
5
400
f
Clock Frequency
Clock Cycle
DQ Burst Frequency
• Intended for 200 and 166 MHz applications
• Inputs and outputs are SSTL-2 compatible
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
QDD
DD
QDD
DD
•V
Description
NT1GD64S8HB0G is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Unbuffered Dual In-Line Memory Module
(UDIMM) and is organized as two ranks of 64Mbx64 high-speed memory array and uses sixteen 64Mx8 DDR SDRAMs TSOP packages.
NT512D64S88B0G is an unbuffered 200-Pin DDR Synchronous DRAM UDIMM and is organized a single rank of 64Mbx64 high-speed
memory array and uses eight 64Mx8 DDR SDRAMs TSOP packages. NT256D64SH4B0G is an unbuffered 200-Pin DDR Synchronous
DRAM UDIMM and is organized a single rank of 32Mbx64 high-speed memory array and uses four 32Mx16 DDR SDRAMs TSOP
packages.
For ECC support, there are two modules that has the addition SDRAM devices that are required. NT1GD72S8PB0G is an unbuffered
200-Pin DDR Synchronous DRAM UDIMM with ECC support and is organized as two ranks of 64Mbx72 high-speed memory array and
uses eighteen 64Mx8 DDR SDRAMs TSOP packages. NT512D72S89B0G is an unbuffered 200-Pin DDR Synchronous DRAM UDIMM
with ECC and is organized a single rank of 64Mbx72 high-speed memory array and uses nine 64Mx8 DDR SDRAMs TSOP packages.
Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves
high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation
type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be
accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.
REV 0.1
May 11, 2004
.eciton tuohtiw snoitacificeps dna stcudorp egnahc ot thgir eht sevreser AYNAN
Preliminary
QD
KC
=V
= 2.5V ± 0.2V (6K); V
=V
= 2.6V ± 0.1V (5T)
1
© NANYA TECHNOLOGY CORPORATION
NT1GD64S8HB0G / NT512D64S88B0G / NT256D64SH4B0G
NT1GD72S8PB0G / NT512D72S89B0G
1GB, 512MB, 256MB, 1GB(ECC) and 512MB(ECC)
Unbuffered DDR DIMM
Ordering Information
Part Number
NT1GD72S8PB0G-5T
Size
Speed
Power
Leads
128Mx72
NT1GD64S8HB0G-5T
128Mx64
NT512MD72S89B0G-5T
DDR400
64x72
Devices
PC3200
200MHz (5ns @ CL = 3)
3-3-3
2.6V
NT512D64S88B0G-5T
64x64
NT256D64SH4B0G-5T
32x64
Gold
NT1GD72S8PB0G-6K
128Mx72
NT1GD64S8HB0G-6K
128Mx64
NT512MD72S89B0G-6K
DDR333
64x72
Devices
PC2700
166MHz (6ns @ CL = 2.5)
2.5-3-3
2.5V
NT512D64S88B0G-6K
64x64
NT256D64SH4B0G-6K
32x64
For the closest sales office or information, please visit:
www.nanya.com
Nanya Technology Corporation
Hwa Ya Technology Park 669
Fu Hsing 3rd Rd., Kueishan,
Taoyuan, 333, Taiwan, R.O.C.
Tel: +886-3-328-1688
REV 0.1
May 11, 2004
2
.eciton tuohtiw snoitacificeps dna stcudorp egnahc ot thgir eht sevreser AYNAN
© NANYA TECHNOLOGY CORPORATION
Preliminary
NT1GD64S8HB0G / NT512D64S88B0G / NT256D64SH4B0G
NT1GD72S8PB0G / NT512D72S89B0G
1GB, 512MB, 256MB, 1GB(ECC) and 512MB(ECC)
Unbuffered DDR DIMM
Pin Description
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0-A9, A11, A12
A10/AP
BA0, BA1
FER
Differential Clock Inputs.
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-precharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
DD
DQ0-DQ63
DQS0-DQS7
DM0-DM7
DD
Data input/output
Bidirectional data strobes
Input Data Mask
Power
Supply voltage for DQs
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply
V
V
NC
SCL
SDA
SA0-2
DPSDD
V
V
V
Identification flag.
V
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
FER
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
SS
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
KEY
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
SS
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
KEY
Back
SS
DQ0
SS
DQ4
DQ5
QDD
A6
DQ28
DQ29
QDD
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
WE
DQ1
DQS0
DQ2
DD
V
DQ25
DQS3
A4
DD
CAS
DQS5
DQ42
DQ43
DD
SS
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
S0
S1
DM0/DQS9
DQ6
DQ7
SS
V
V
DM3/DQS12
A3
DQ30
SS
DM5/DQS14
SS
V
V
V
DQ3
NC
NC
SS
V
DQ26
DQ27
A2
SS
DQ46
DQ47
NC
QDD
NC
NC
NC
QDD
V
V
DQ31
NC
NC
QDD
NC
DQ48
DQ49
CK2
CK2
QDD
SS
V
V
V
DQ8
DQ9
DQS1
QDD
V
A1
NC
NC
DD
DQ52
DQ53
NC
DD
DQ12
DQ13
DM1/DQS10
DD
V
V
CK0
CK0
NC
A10
NC
QDD
SS
V
V
V
CK1
CK1
DQ10
DQ11
CKE0
QDD
SS
V
NC
A0
NC
SS
V
V
DM6/DQS15
DQ54
DQ55
QDD
DQ14
DQ15
CKE1
QDD
DQS6
DQ50
DQ51
SS
V
V
V
V
NC
BA1
V
V
NC
DQ60
DQ61
SS
V
DQ20
A12
SS
DQ56
DQ57
DD
DQS2
SS
DQ21
A11
DM2/DQS11
DD
DQ33
DQS4
DQ34
SS
A7
QDD
DQ22
A8
DQ23
BA0
DQ35
DQ40
151
152
153
DQ39
SS
90
91
92
WP
SDA
SCL
V
V
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 0.1
May 11, 2004
3
.eciton tuohtiw snoitacificeps dna stcudorp egnahc ot thgir eht sevreser AYNAN
© NANYA TECHNOLOGY CORPORATION
Preliminary
DPSDD
DQ19
DQ44
SS
DQ18
V
V
150
DQ38
89
V
SA0
SA1
SA2
V
QDD
A9
149
DM4/DQS13
DD
V
QDD
DQ17
V
V
146
147
148
DQ36
DQ37
V
SS
DQ16
DQ32
145
V
84
85
86
87
88
V
DQS7
DQ58
DQ59
DIDD
NC
NC
V
V
DM7/DQS16
DQ62
DQ63
V
QDD
V
V
DQ41
QDD
V
V
V
SS
V
QDD
DIDD
Pin
62
Front
V
Pin
154
155
156
Back
RAS
DQ45
V
NT1GD64S8HB0G / NT512D64S88B0G / NT256D64SH4B0G
NT1GD72S8PB0G / NT512D72S89B0G
1GB, 512MB, 256MB, 1GB(ECC) and 512MB(ECC)
Unbuffered DDR DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
(SSTL)
Type
Polarity
Cross
point
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
S0, S1
(SSTL)
Active
Low
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
RAS, CAS, WE
FER
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock,
RAS, CAS, WE
define the operation to
be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
V
V
BA0, BA1
A0 - A9
A10/AP
A11, A12
DQ0 - DQ63
DQS0 - DQS7,
DQS9 – DQS16
CB0 – CB7
DM0 – DM8
V ,V
DD
SA0 – SA2
SDA
SCL
DPSDD
Presence Detect EEPROM address.
-
-
Supply
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
V
REV 0.1
May 11, 2004
4
© NANYA TECHNOLOGY CORPORATION
.eciton tuohtiw snoitacificeps dna stcudorp egnahc ot thgir eht sev
reser AYNAN
Preliminary
SS
DD
SS
QDD
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
or V
on the system board to configure the Serial
(SSTL)
-
(SSTL)
(SSTL)
(SSTL)
Input
Supply
-
Active
High
-
Active
High
-
NT1GD64S8HB0G / NT512D64S88B0G / NT256D64SH4B0G
NT1GD72S8PB0G / NT512D72S89B0G
1GB, 512MB, 256MB, 1GB(ECC) and 512MB(ECC)
Unbuffered DDR DIMM
Functional Block Diagram
2 Ranks, 18 devices, 64Mx8 DDR SDRAMs, NT1GD72S8PB0G
S1
S0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQS4
DM4/DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D0
D9
D4
D13
D1
D10
D5
D14
D2
D11
D6
D15
D3
D12
D7
D16
D8
D17
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
BA0-BA1
A0-A13
RAS
CAS
CKE0
CKE1
WE
BA0-BA1 : SDRAMs D0-D17
A0-A13 : SDRAMs D0-D17
RAS
: SDRAMs D0-D17
CAS
: SDRAMs D0-D17
CKE : SDRAMs D0-D8
CKE : SDRAMs D9-D17
WE
: SDRAMs D0-D17
REV 0.1
May 11, 2004
5
.eciton tuohtiw snoitacificeps dna stcudorp egnahc ot thgir eht sevreser AYNAN
© NANYA TECHNOLOGY CORPORATION
Preliminary
QDD
DD
QDD
QDD
DD
DD
SS
DIDD
Notes :
1.
2.
3.
4.
DQ-to-I/O wring may be changed within a byte.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22 Ohms.
V
strap connections (for memory device V , V ):
STRAP OUT (OPEN): V = V
STRAP IN (V ): V is not equal to V .
smargaiD gniriW
/elbaT gnidaoL kcolC rep eriW *
DIDD
SS
FER
QDD DD
DPSDD
V
V /V
V
V
V
SPD
D0-D8
D0-D8
D0-D8
Strap: see Note 4
* Clock Wiring
Clock Input
SDRAMs
*CK0/CK0
6 SDRAMs
*CK1/CK1
6 SDRAMs
*CK2/CK2
6 SDRAMs
测试/测量
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