NT128D64SH4B1G
NT128D64SH4B1GY
128MB : 16M x 64
PC3200 Unbuffered DDR DIMM
184pin Unbuffered DDR DIMM
Based on DDR400 16Mx16 SDRAM
Features
• 16Mx64 Unbuffered DDR DIMM based on 16Mx16 DDR
SDRAM
• JEDEC Standard 184-pin Dual In-Line Memory Module
• Performance:
PC3200A PC3200B
Speed Sort
DIMM
CAS
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
f
DQ
DQ Burst Frequency
-5
2.5
200
5
400
-5T
3
200
5
400
MHz
ns
MHz
Unit
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2.5, 3
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/9/1 Addressing (row/column/bank)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
• Lead-free and Halogen-free product available
• Intended for 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= 2.6Volt ± 0.1, V
DDQ
= 2.6Volt ± 0.1
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
Description
NT128D64SH4B1G and NT128D64SH4B1GY are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line
Memory Modules (DIMM), organized as a one-bank 16Mx64 high-speed memory array. The module uses four 16Mx16 DDR SDRAMs in
400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs.
The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a
high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to
400 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
NT128D64SH4B1G-5
Speed
200MHz (5ns @ CL = 2.5)
166MHz (6ns @ CL = 2.5)
200MHz (5ns @ CL = 3)
166MHz (6ns @ CL = 2.5)
200MHz (5ns @ CL = 2.5)
166MHz (6ns @ CL = 2.5)
200MHz (5ns @ CL = 3)
166MHz (6ns @ CL = 2.5)
DDR400A
PC3200A
Organization
16Mx64
Leads
Gold
Power
2.6V
NT128D64SH4B1G-5T
DDR400B
PC3200B
16Mx64
Gold
2.6V
NT128D64SH4B1GY-5*
DDR400A
PC3200A
16Mx64
Gold
2.6V
NT128D64SH4B1GY-5T*
DDR400B
PC3200B
16Mx64
Gold
2.6V
* Lead-free and Halogen-free product
REV 1.1
06/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B1G
NT128D64SH4B1GY
128MB : 16M x 64
PC3200 Unbuffered DDR DIMM
Pin Description
CK1, CK2,
CK1, CK2
CKE0
RAS
CAS
WE
S0
A10/AP
BA0, BA1
V
REF
V
DDID
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
(Not used when V
DD
=V
DDQ)
DQ0-DQ63
DQS0-DQS7
DM0-DM7
VDD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bi-directional data strobes
Data Masks
Power (2.6V)
Supply voltage for DQs (2.6V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply (2.6V)
A0-A9, A11, A12 Address Inputs
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
CK1
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
V
SS
DQ4
DQ5
V
DDQ
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
NC
V
DDQ
NC
DQ20
NC
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
53
54
55
56
57
58
59
60
61
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
KEY
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
Front
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
NC
A0
NC
V
SS
NC
BA1
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Back
V
SS
A6
DQ28
DQ29
V
DDQ
DQS12
A3
DQ30
V
SS
DQ31
NC
NC
V
DDQ
CK0
CK0
V
SS
NC
A10
NC
V
DDQ
NC
KEY
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
V
DDQ
WE
DQ41
CAS
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
CK2
CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
V
DDQ
S0
NC
DQS14
V
SS
DQ46
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.1
06/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B1G
NT128D64SH4B1GY
128MB : 16M x 64
PC3200 Unbuffered DDR DIMM
Input/Output Functional Description
Symbol
CK1, CK2
CK1, CK2
CKE0
Type
(SSTL)
(SSTL)
(SSTL)
Polarity
Function
Positive The positive line of the differential pair of system clock inputs. All the DDR SDRAM
Edge address and control inputs are sampled on the rising edge of their associated clocks.
Negative
The negative line of the differential pair of system clock inputs.
Edge
Active
High
Active
Low
Active
Low
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
RAS, CAS, WE
define the operation
to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
-
-
-
Supply
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
S0
RAS, CAS, WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
A0 - A9
A10/AP
A11, A12
(SSTL)
-
DQ0 - DQ63
DQS0 - DQS7
DQS9 - DQS16
V
DD,
V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
(SSTL)
(SSTL)
Supply
-
Active
High
REV 1.1
06/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B1G
NT128D64SH4B1GY
128MB : 16M x 64
PC3200 Unbuffered DDR DIMM
Functional Block Diagram
(1 Bank, 16Mx16 DDR SDRAMs)
S0
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
D0
CS
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
D2
CS
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
CS
D1
D3
BA0-BA1
A0-A13
RAS
CAS
CKE0
WE
BA0-BA1 : SDRAMs D0-D3
A0-A13 : SDRAMs D0-D3
RAS
: SDRAMs D0-D3
CAS
: SDRAMs D0-D3
CKE : SDRAMs D0-D3
WE
: SDRAMs D0-D3
Serial PD
V
DDSPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
SPD
D0-D3
D0-D3
D0-D3
Strap: see Note 4
* Clock Wiring
Clock Input
SDRAMs
*CK0/CK0
NC
*CK1/CK1
2 SDRAMs
*CK2/CK2
2 SDRAMs
* Wire per Clock Loading Table/
Wiring Diagrams
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
Notes :
1.
2.
3.
4.
DQ-to-I/O wiring is shown as recommended but may be changed.
DQ/DQS/DM/CKE/S relationships must be maintained as shown.
DQ, DQS, DM/DQS resistors: 22 Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.1
06/2003
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B1G
NT128D64SH4B1GY
128MB : 16M x 64
PC3200 Unbuffered DDR DIMM
Serial Presence Detect --
Part 1 of 2
16Mx64 SDRAM DIMM based on 16Mx16, 4Banks, 8K Refresh, 2.6V DDR SDRAMs with SPD
SPD Entry Value
Byte
Description
DDR400A
-5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=3
DDR SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
DDR SDRAM Device Attributes: Burst Length Supported
DDR SDRAM Device Attributes: Number of Device Banks
DDR SDRAM Device Attributes: CAS Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2.5
Maximum Data Access Time from Clock at CL=2.5
Minimum Clock Cycle Time at CL=2
Maximum Data Access Time from Clock at CL=2
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
Minimum Active/Auto-Refresh Time (t
RC
)
SDRAM Device Minimum Auto-Refresh to
Active/Auto-Refresh Command Period (t
RFC
)
SDRAM Device Maximum Cycle Time (t
CK
max)
SDRAM Device DQS-DQ Skew Time (t
DQSQ
)
SDRAM Device Maximum Read Data Hold Skew Factor
(t
QHS
)
Superset Information (Reserved)
SPD Revision
Checksum Data
0.6ns
0.6ns
0.4ns
0.4ns
55ns
70ns
8
0.4
0.5
Undefined
Initial
Initial
00
67
2.5/3
0
1
Differential Clock
+/-0.1V Voltage Tolerance
5ns
0.6ns
N/A
N/A
15ns
10ns
15ns
40ns
128MB
0.6ns
0.6ns
0.4ns
0.4ns
55ns
70ns
8
0.4
0.5
60
60
40
40
00
37
46
20
28
50
00
00
75
37
46
20
28
50
6ns
0.7ns
7.5ns
7.5ns
15ns
10ns
15ns
40ns
50
60
00
00
3C
28
3C
28
20
60
60
40
40
5ns
0.60ns
128
256
SDRAM DDR
13
9
1
X64
X64
SSTL 2.5V
5ns
0.60ns
Non-Parity
SR/1x(7.8us)
X16
N/A
1 Clock
2,4,8
4
2/2.5/3
18
01
02
20
00
60
70
75
75
3C
28
3C
28
50
60
00
82
10
00
01
0E
04
1C
DDR400B
-5T
Serial PD Data Entry
(Hexadecimal)
DDR400A
-5
80
08
07
0D
09
01
40
00
04
50
60
DDR400B
-5T
Note
Undefined
REV 1.1
06/2003
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
