NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Based on DDR3-1066/1333/1600 128Mx16 (1GB) / 256Mx8 (2GB) / 256Mx8 (4GB) SDRAM B-Die
Features
•Performance:
Speed Sort
DIMM CAS Latency
fck – Clock Frequency
tck – Clock Cycle
fDQ – DQ Burst Frequency
PC3-8500
-BE
7
533
1.875
1066
PC3-10600
-CG
9
667
1.5
1333
PC3-12800
-DI
11
800
1.25
1600
MHz
ns
Mbps
• Programmable Operation:
- DIMM
Latency: 5, 6, 7, 8/PC3-8500; 5, 6, 7, 8,
9/PC3-10600; 5, 6, 7, 8, 9, 10, 11/PC3-12800
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
• Two different termination values (Rtt_Nom & Rtt_WR)
• 14/10/1 (row/column/rank) Addressing for 1GB
• 15/10/1 (row/column/rank) Addressing for 2GB
• 15/10/2 (row/column/rank) Addressing for 4GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• 1GB: SDRAMs are in 96-ball BGA Package
• 2GB: SDRAMs are in 78-ball BGA Package
• 4GB: SDRAMs are in 78-ball BGA Package
• RoHS compliance + Halogen Free
Unit
• 204-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 1GB: 128Mx64 Unbuffered DDR3 SO-DIMM based on 128Mx16
DDR3 SDRAM B-Die devices.
• 2GB: 256Mx64 Unbuffered DDR3 SO-DIMM based on 256Mx8
DDR3 SDRAM B-Die devices.
•4GB: 512Mx64 Unbuffered DDR3 SO-DIMM based on 256Mx8
DDR3 SDRAM B-Die devices.
• Intended for 533MHz/667MHz/800MHz applications
• Inputs and outputs are SSTL-15 compatible
• V
DD
= V
DDQ
= 1.5V ±0.075V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
Description
NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS are un-buffered 204-Pin Double Data Rate 3 (DDR3) Synchronous DRAM
Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 128Mx64 (1GB) and one rank of 256Mx64 (2GB) /
512Mx64 (4GB) high-speed memory array. Modules use four 128Mx16 (1GB) 96-ball BGA packaged devices and eight 256Mx8 (2GB)
78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw
cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All NANYA DDR3 SODIMMs provide a high-performance, flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz/800MHz clock speeds and achieves high-speed data transfer
rates of 1066Mbps/1333Mbps/1600Mbps. Prior to any access operation, the device
latency and burst/length/operation type must be
programmed into the DIMM by address inputs A0-A13 (1GB)/A0-A14 (2GB/4GB) and I/O inputs BA0~BA2 using the mode register set
cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.1
08/2010
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Ordering Information
Part Number
NT1GC64BH4B0PS-BE
NT1GC64BH4B0PS-CG
NT1GC64BH4B0PS-DI
NT2GC64B88B0NS-BE
NT2GC64B88B0NS-CG
NT2GC64B88B0NS-DI
NT4GC64B8HB0NS-BE
NT4GC64B8HB0NS-CG
NT4GC64B8HB0NS-DI
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1066
DDR3-1333
DDR3-1600
PC3-8500
Speed
533MHz (1.875ns @ CL = 7)
128Mx64
Organization
Power
Leads
Note
PC3-10600 667MHz (1.5ns @ CL = 9)
PC3-12800 800MHz(1.25ns @ CL=11)
PC3-8500
533MHz (1.875ns @ CL = 7)
PC3-10600 667MHz (1.5ns @ CL = 9)
PC3-12800 800MHz(1.25ns @ CL=11)
PC3-8500
533MHz (1.875ns @ CL = 7)
256Mx64
1.5V
Gold
PC3-10600 667MHz (1.5ns @ CL = 9)
PC3-12800 800MHz(1.25ns @ CL=11)
512Mx64
Pin Description
Pin Name
CK0, CK1
,
CKE0, CKE1
,
A10/AP
A12/
BA0-BA2
ODT0, ODT1
SCL
SDA
Description
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Input/Auto-Precharge
Address Input/Burst Chop
SDRAM Bank Address Inputs
Active termination control lines
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Pin Name
DQ0-DQ63
DQS0-DQS7
-
DM0-DM7
V
REFDQ
, V
REFCA
V
DDSPD
SA0, SA1
Vtt
V
SS
V
DD
NC
Data strobes
Data strobes complement
Data Masks
Temperature event pin
Reset pin
Input/Output Reference
SPD and Temp sensor power
Serial Presence Detect Address Inputs
Termination voltage
Ground
Core and I/O power
No Connect
Description
Data input/output
A0-A9, A11, A13-A15 Address Inputs
Note: A14 is for 2GB and 4GB modules only.
REV 1.1
08/2010
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
DDR3 SDRAM Pin Assignment
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Front
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DM0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2
V
SS
DQ18
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Back
V
SS
DQ4
DQ5
V
SS
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
V
SS
DQ22
DQ23
Pin
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
Front
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12/
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
Pin
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
Back
V
SS
DQ28
DQ29
V
SS
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
A15/NC
A14/NC
V
DD
A11
A7
V
DD
A6
A4
V
DD
A2
A0
V
DD
CK1
Pin
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
Front
V
DD
A10/AP
BA0
V
DD
V
DD
A13/NC
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
Pin
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
Back
V
DD
BA1
V
DD
ODT0
V
DD
ODT1
NC
V
DD
V
REFCA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
Pin
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
Vtt
Pin
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Back
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7
V
SS
DQ62
DQ63
V
SS
SDA
SCL
Vtt
201
DQS5
203
Note: A14 is for 2GB and 4GB modules only.
REV 1.1
08/2010
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Input / Output Functional Description
Symbol
CK0, CK1
,
CKE0, CKE1
,
,
,
ODT0, ODT1
DM0 – DM7
Type
Input
Input
Input
Polarity
Cross
point
Active
High
Active
Low
Active
Low
Active
High
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of
.
A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by
;
Rank 1 is selected by
When sampled at the positive rising edge of CK and falling edge of
,
signals
,
,
define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and
signals if enabled via the DDR3 SDRAM
mode register.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
signals are complements, and timing is relative to the cross point of respective DQS and
.
If the module is to be operated in single ended strobe mode, all
signals must be tied on
the system board to V
SS
and DDR3 SDRAM mode registers programmed appropriately.
Selects which DDR3 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of
.
During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
.
In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
Data Input/Output pins.
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a pull
up.
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The
pin is reserved for use to flag critical module temperature.
This signal resets the DDR3 SDRAM
Reference pin for ZQ calibration
Input
Input
Input
DQS0 – DQS7
–
I/O
Cross
point
BA0, BA1, BA2
Input
-
A0 – A9
A10/AP
A11
A12/
A13 – A15
Input
-
DQ0 – DQ63
V
DD
,
V
DDSPD,
V
SS
V
REFDQ,
V
REFCA
SDA
SCL
SA0 – SA2
ZQ
Input
Supply
Supply
-
-
-
-
-
-
-
-
-
I/O
Input
Input
Output
Input
Supply
REV 1.1
08/2010
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
NT1GC64BH4B0PS / NT2GC64B88B0NS / NT4GC64B8HB0NS
1GB: 128M x 64 / 2GB: 256M x 64 / 4GB: 512M x 64
PC3-8500 / PC3-10600 / PC3-12800
Unbuffered DDR3 SO-DIMM
Functional Block Diagram
[1GB
–
1 Rank, 128Mx16 DDR3 SDRAMs]
CK0
CKE0
ODT0
A[0:13]/BA[0:2]
CK
CKE
ODT
A[0:13]/BA[0:2]
DQS2
DM2
DQ[16:31]
DQS3
DM3
CK
CKE
ODT
A[0:13]/BA[0:2]
DQS0
DM0
DQ[0:15]
DQS1
DM1
LDQS
L
LDM
DQ[0:15]
UDQS
UDM
240ohm
+/-1%
ZQ
D0
LDQS
L
LDM
DQ[0:15]
UDQS
UDM
240ohm
+/-1%
ZQ
SCL
D1
SA0
SA1
SCL
A0
A1
A2
SPD
WP
SDA
Vtt
CK
CKE
ODT
A[0:13]/BA[0:2]
DQS6
DM6
DQ[48:63]
DQS7
DM7
CK
CKE
ODT
A[0:13]/BA[0:2]
DQS4
DM4
DQ[32:47]
DQS5
DM5
LDQS
L
LDM
DQ[0:15]
UDQS
UDM
240ohm
+/-1%
ZQ
D2
Vtt
V
DDSPD
V
REFCA
V
REFDQ
V
DD
V
SS
CK0
CK1
Vtt
SPD
D0-D7
D0-D7
D0-D7
D0-D7, SPD
D0-D3
D0-D3
D4-D7
D4-D7
D0-D7
LDQS
L
LDM
DQ[0:15]
UDQS
UDM
240ohm
+/-1%
ZQ
Notes :
D3
1. DQ wiring may differ from that shown however, DQ, DM,
DQS, and
relationships
are maintained as shown.
Vtt
VDD
REV 1.1
08/2010
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
stm32/stm8
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