TMU3102
USB Controller
GENERAL DESCRIPTION
The TMU3102 is an 8-bit microprocessor embedded device tailored to the USB genernal purpose application.
It includes an 8-bit RISC CPU core, 192-byte SRAM, Low Speed USB Interface and an 8K x 14 internal
program OTP-ROM.
FEATURE
Compliance with the Universal Serial Bus specification v1.1
Built-in USB Transceiver without external pull-up resister and 3.3V regulator
Support USB Suspend and Resume function
One Control IN/OUT and one Interrupt IN endpoints
PS2 compatible mouse interface share with USB interface
192 byte internal SRAM
8K x 14 internal program OTP-ROM.
8-bit RISC CPU core with only 36 instruction
Internal Oscillator 6MHz±1.5% operation without external components.
3MHz instruction rate with 6MHz crystal oscillation.
Support internal wake up timer for power saving.
18/20/24 pin PDIP/SOP package
BLOCK DIAGRAM
USB
Transceiver
USB
SIE
USB
Controller
Input
Interface
8K x 14
Program OTP
ROM
8-bit RISC
CPU
192 Bytes
SRAM
1
tenx technology, inc.
Rev 1.2 2006/03/17
TMU3102
PIN DESCRIPTION
Name
VDD
VSS
X1
RC6M
VPP
V33
DP/PB[3]
DM/PB[2]
PB[1:0]/
PB[7:4]
PD[7:0]
I/O
P
P
I
O
I
O
Description
5V Power from USB cable
Ground
Test/OTP mode clock in
Internal clock output (6MHz)
OTP programming power
3.3V regulator output
I/O USB positive data signal / General purpose I/O (pseudo open-drain)
I/O USB negative data signal / General purpose I/O (pseudo open-drain)
I/O General purpose I/O (pseudo open-drain)
I/O Multi-function I/O (pseudo open-drain, Push-pull output, Input from pin or comparator.)
PIN ASSIGNMENT
PD[0]
PD[1]
PD[2]
PD[3]
PB[0]
VSS
VPP
V33
X1
1
2
3
4
5
6
7
8
9
TMU3102
18 pin
18
17
16
15
14
13
12
11
10
PD[4]
PD[5]
PD[6]
PD[7]
PB[1]
DP/PB[3]
DM/PB[2]
VDD
RC6M
PD[0]
PD[1]
PD[2]
PD[3]
PB[4]
PB[0]
VSS
VPP
V33
X1
1
2
3
4
5
6
7
8
9
10
TMU3102
20 pin
20
19
18
17
16
15
14
13
12
11
PD[4]
PD[5]
PD[6]
PD[7]
PB[1]
PB[5]
DP/PB[3]
DM/PB[2]
VDD
RC6M
PD[0]
PD[1]
PD[2]
PD[3]
PB[4]
PB[6]
PB[0]
N.C.
VSS
VPP
V33
X1
1
2
3
4
5
6
7
8
9
10
11
12
TMU3102
24 pin
24
23
22
21
20
19
18
17
16
15
14
13
PD[4]
PD[5]
PD[6]
PD[7]
PB[1]
PB[5]
PB[7]
N.C.
DP/PB[3]
DM/PB[2]
VDD
RC6M
2
tenx technology, inc.
Rev 1.2 2006/03/17
TMU3102
FUNCTIONAL DESCRIPTION
1. CPU Core
1.1
Clock Scheme and Instruction Cycle
The clock input (X1) is internally divided by two to generate Q1 state and Q2 state for each instruction cycle.
The Programming Counter (PC) is updated at Q1 and the instruction is fetched from program ROM and
latched into the instruction register in Q2. It is then decoded and executed during the following Q1-Q2 cycle.
1.2
Programming Counter (PC) and Stack
The Programming Counter is 13-bit wide capable of addressing a 8K x 14 program ROM. As a program
instruction is executed, the PC will contain the address of the next program instruction to be executed. The
PC value is normally increased by one except the followings. The Reset Vector (0) and the Interrupt Vector
(1) are provided for PC initialization. For CALL/GOTO instructions, PC loads its lower 12 bits from instruction
word and the MSB from STATUS’s bit 6. For RET/RETI/RETLW instructions, PC retrieves its content from
the top level STACK. For the other instructions updating PC[7:0], the PC[12:8] keeps unchanged.
The STACK is 13-bit wide and 6-level in depth. The CALL instruction and Hardware interrupt will push
STACK level in order, While the RET/RETI/RETLW instruction pops the STACK level in order.
1.3
Addressing Mode
There are two Data Memory Plane in CPU, R-Plane and F-Plane. The registers in R-Plane are write-only.
The “MOVWR” instruction copy the W-register’s content to those registers by direct addressing mode.
Registers in F-Plane can be addressed directly or indirectly. Indirect Addressing is made by address “0”,
where FSR points to an actual address. The first half of F-Plane is also bit-addressable.
Program Memory
0000
0001
Reset Vector
Interrupt Vector
Program ROM Page 0
STATUS.6=0
0fff
1000
Program ROM Page 1
STATUS.6=1
3f
00
R-Plane
00
F-Plane
Registers, STATUS.4=0/1
Bit addressable
MOVWR Instruction
Write Only
1f
20
RAM, STATUS.4=0 RAM, STATUS.4=1
Bit addressable
Bit addressable
3f
40
RAM, STATUS.4=0 RAM, STATUS.4=1
1fff
7f
3
tenx technology, inc.
Rev 1.2 2006/03/17
TMU3102
1.4
ALU and Working (W) Register
The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. In two-operand
instructions, typically one operand is the W register, which is an 8-bit non-addressable register used for ALU
operations. The other operand is either a file register or an immediate constant. In single operand
instructions, the operand is either W register or a file register.
Depending on the instruction executed, the ALU may affect the values of Carry(C), Digit Carry(DC), and
Zero(Z) Flags in the STATUS register. The C and DC flags operate as a /Borrow and /Digit Borrow,
respectively, in subtraction.
1.5
STATUS Register
This register contains the arithmetic status of ALU and the page select for Program ROM and Data RAM.
The STATUS register can be the destination for any instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits
is disabled. These bits are set or cleared according to the device logic. It is recommended, therefore, that
only BCF, BSF and MOVWF instructions be used to alter the STATUS Register because these instructions
do not affect those bits.
1.6
Interrupt
Each interrupt source has its own enable control bit. An interrupt event will set its individual flag. If the
corresponding interrupt enable bit has been set, it would trigger CPU to service the interrupt. CPU accepts
interrupt in the end of current executed instruction cycle. In the mean while, A “CALL 0001” instruction is
inserted to CPU, and the I-flag is set to prevent recursive interrupt nesting. The I-flag is cleared in the
instruction after the “RETI” instruction. That is, at least one instruction in main program is executed before
service the pending interrupt. The interrupt event is level trigged. F/W must clear the interrupt event register
while serves the interrupt routine.
1.7
Instruction Set
Each instruction is a 14-bit word divided into an OPCODE, which specified the instruction type, and one or
more operands, which further specify the operation of the instruction. The instructions can be categorized as
byte-oriented, bit-oriented and literal operations list in the following table.
For byte-oriented instructions, “f” represents address designator and “d” represents destination designator.
The address designator is used to specify which address in F-Plane is to be used by the instruction. The
destination designator specifies where the result of the operation is to be placed. If “d” is “0”, the result is
placed in the W register. If “d” is “1”, the result is placed in the address specified in the instruction.
For bit-oriented instructions, “b” represents a bit field designator, which selects the number of the bit affected
by the operation, while “f” represents the address designator.
For literal operations, “k” represents the literal or constant value.
For “MOVWR” instruction, “r” specifies which address in R-Plane is to be used by the instruction.
All instructions are single cycle except for program branches, which are two-cycle.
4
tenx technology, inc.
Rev 1.2 2006/03/17
TMU3102
Mnemonic
NOP
SLEEP
CLRWDT
MOVWR r
RET
RETI
MOVWF f
CLRW
CLRF f
SUBWF f,d
DECF f,d
IORWF f,d
ANDWF f,d
XORWF f,d
ADDWF f,d
MOVFW f
TESTZ f
COMF f,d
INCF f,d
DECFSZ f,d
RRF f,d
RLF f,d
SWAPF f,d
INCFSZ f,d
BCF f,b
BSF f,b
BTFSC f,b
BTFSS f,b
RETLW k
MOVLW k
IORLW k
ANDLW k
ADDLW k
XORLW k
CALL k
GOTO k
Op Code
00 0000 0 0000000
00 0000 0 0000011
00 0000 0 0000100
00 0000 0 0rrrrrr
00 0000 0 1000000
00 0000 0 1100000
00 0000 1 fffffff
00 0001 0 1000000
00 0001 1 fffffff
00 0010 d fffffff
00 0011 d fffffff
00 0100 d fffffff
00 0101 d fffffff
00 0110 d fffffff
00 0111 d fffffff
00 1000 0 fffffff
00 1000 1 fffffff
00 1001 d fffffff
00 1010 d fffffff
00 1011 d fffffff
00 1100 d fffffff
00 1101 d fffffff
00 1110 d fffffff
00 1111 d fffffff
010 00 bbb ffffff
010 01 bbb ffffff
010 10 bbb ffffff
010 11 bbb ffffff
011 000 kkkkkkkk
011 001 kkkkkkkk
011 010 kkkkkkkk
011 011 kkkkkkkk
011 100 kkkkkkkk
011 111 kkkkkkkk
10 kkkk kkkkkkkk
11 kkkk kkkkkkkk
Flag
Cycles Affect
Description
1
-
No operation
1
Go into standby mode, Clock oscillation stops
1
Clear and enable Watch Dog Timer
1
-
Move W to “r”
2
-
Return
2
-
Return from interrupt
1
-
Move W to “f”
1
Z
Clear W
1
Z
Clear “f”
1
C,DC,Z Subtract W from “f”
1
Z
Decrement “f”
1
Z
OR W with “f”
1
Z
AND W with “f”
1
Z
XOR W with “f”
1
C,DC,Z Add W and “f”
1
-
Move “f” to “w”
1
Z
Test if “f” is zero
1
Z
Complement “f”
1
Z
Increment “f”
1 or 2
-
Decrement “f”, skip if zero
1
C
Rotate right “f” through carry
1
C
Rotate left “f” through carry
1
-
Swap high/low nibble of “f”
1 or 2
-
Increment “f”, skip if zero
1
-
Clear “b” bit of “f”
1
-
Set “b” bit of “f”
1 or 2
-
Test “b” bit of “f”, skip if clear
1 or 2
-
Test “b” bit of “f”, skip if set
2
-
Return, place Literal “k” in W
1
-
Move Literal “k” to W
1
Z
OR Literal “k” with W
1
Z
AND Literal “k” with W
1
C,DC,Z Add Literal “k” to W
1
Z
XOR Literal “k” with W
2
-
Call subroutine “k”
2
-
Jump to branch “k”
5
tenx technology, inc.
Rev 1.2 2006/03/17
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