DDR2 PC2-xx00
ECC REGISTERED SODIMM
VR5DRxx7218xxx
Module Configuration
V/I Part Number
VR5DR647218EBP
VR5DR647218EBS
VR5DR647218EBW
VR5DR647218EBZ
VR5DR647218EBY
VR5DR287218EBP
VR5DR287218EBS
VR5DR287218EBW
VR5DR287218EBZ
VR5DR287218EBY
VR5DR287218FBP
VR5DR287218FBS
VR5DR287218FBW
VR5DR287218FBZ
VR5DR287218FBY
VR5DR567218FBP
VR5DR567218FBS
VR5DR567218FBW
VR5DR567218FBZ
VR5DR567218FBY
VR5DR127218GBP
VR5DR127218GBS
VR5DR127218GBW
VR5DR127218GBZ
VR5DR127218GBY
Capacity
512MB
512MB
512MB
512MB
512MB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
Module
Configuration
64Mx72
64Mx72
64Mx72
64Mx72
64Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
Device
Configuration
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (9)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
64M x 8 (18)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (9)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
128M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
256M x 8 (18)
Device
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
Module
Ranks
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
Performance
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
PC2-3200
PC2-4200
PC2-5300
PC2-6400
PC2-6400
CAS
Latency
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
Features
•
•
•
•
•
•
•
•
•
•
•
200 pin Registered SO-DIMM JEDEC pin out
Single 1.8V
±
0.1V Power Supply
Burst Length (4, 8)
Burst type (Sequential & Interleave)
Auto & Self-Refresh.
7.8 µs Average Refresh Period.
Differential CLK (#CLK) input.
On-die termination (ODT)
Off-chip driver (OCD) impedance adjustment
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DRxx7218xxx Revision E Created By: Brian Ouellette
Page 1 of 17
DDR2 PC2-xx00
ECC REGISTERED SODIMM
VR5DRxx7218xxx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
#CK0
TYPE
IN
POLARITY
Positive Edge
Negative Edge
DESCRIPTION
CKE0 ~ CKE1
IN
Active High
#S0 ~ #S1
IN
Active Low
ODT0 ~ ODT1
#RAS, #CAS,
#WE
VREF
VDD, VDDQ
BA [2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A [n:0]
IN
-
Clock: CK and #CK are differential clock inputs. All addresses and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of #CK. Output data (DQs, DQS and #DQS) is referenced to the crossings
of CK and #CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers of the SDRAMs. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables
decoder when high. When decoder is disabled, new commands are ignored and
previous operations continue. These input signals also disable all outputs
(except CKE and ODT) of the register(s) on the DIMM when both inputs are
high. When both S[0:1] are high, all register outputs (except CKE, ODT and
Chip select) remain in the previous state.
On-Die Termination control signals
CAS, WE When sampled at the positive rising edge of the clock, /CAS, /RAS,
and /WE define the operation to be executed by the SDRAM.
Reference voltage for SSTL18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved
noise immunity
Selects which SDRAM bank of four or eight is activated.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In
addition to the column address, AP is used to invoke autoprecharge operation at
the end of the burst read or write cycle. If AP is high, autoprecharge is selected
and BA0, BA1, BA2 defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in
conjunction with BA0, BA1,BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2.
If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge.
Data and Check Bit Input/Output pins
Masks write data when high, issued concurrently with input data.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD to
configure the serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A
resistor must be connected from the SDA bus line to VDDSPD on the system
planar to act as a pullup.
Serial EEPROM positive power supply (wired to a separate power pin at the
connector which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and
3.3 Volt) operations.
DQ [63:0],
CB [7:0]
DM [8:0]
DQS [8:0]
#DQS [8:0]
SA [1:0]
SDA
I/O
IN
I/O
I/O
IN
I/O
-
Active High
Positive Edge
Negative Edge
-
-
VDDSPD
Supply
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5DRxx7218xxx Revision E Created By: Brian Ouellette
Page 3 of 17
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