NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
Based on DDR2-667/800 128Mx8 (1GB/2GB) and 256MX4 (2GB/4GB) SDRAM D-Die
Features
• 1GB/2GB: 128Mx72/256Mx72 Registered DDR2 DIMM based
on 128Mx8 DDR2 SDRAM. (NT5TU128M8DE)
• 2GB/4GB: 256Mx72/512MX72 Registered DDR2 DIMM based
on 256Mx4 DDR2 SDRAM. (NT5TU256M4DE)
• 240-Pin Registered Dual In-Line Memory Module (RDIMM)
• Error Check Correction (ECC) Support
• Phase-lock loop (PLL) clock driver to reduce loading
• Performance:
Speed Sort
DIMM
Latency
PC2-5300 PC2-6400
-3C
5
333
3
667
-AD
6
400
2.5
800
MHz
ns
Mbps
Unit
• Differential clock inputs
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
• Programmable Operation:
- Device
Latency: 3,4,5,6
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 14/11/2 (row/column/rank) Addressing for 4GB
14/11/1 (row/column/rank) Addressing for 2GB
14/10/1 (row/column/rank) Addressing for 1GB/2GB
• Serial Presence Detect
• Gold contacts
• SDRAMs in 60-ball BGA Package
• RoHS Complianc
fck – Clock Freqency
tck – Clock Cycle
fDQ – DQ Burst Freqency
• Intended for 333MHz & 400MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= 1.8Volt ± 0.1Volt, V
DDQ
= 1.8Volt ± 0.1Volt
• SDRAMs have 8 internal banks for concurrent operation
• One clock cycle added for registered DIMMs to account for
input register
Description
NT1GT72U89D0BV, NT2GT72U4PD0BV, NT2GT72U8PD0BV and NT4GT72U4ND0BV are Registered 240-Pin Double Data Rate 2
(DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one rank 128Mx72, 256Mx72 high-speed memory
array and two ranks 512MX72 high-speed memory array. The module uses nine 128Mx8 (NT1GT72U89D0BV), eighteen 128Mx8
(NT2GT72U8PD0BV), eighteen 256Mx4 (NT2GT72U4PD0BV) and thirty-six 256Mx4 (NT4GT72U4ND0BV) DDR2 SDRAMs in BGA
packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these
common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 333 MHz (or 400 MHz) clock speeds and achieves high-speed data transfer
rates of up to 667Mbps (or 800Mbps ). Prior to any access operation, the device
latency and burst/length/operation type must be
programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1, and BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.1
01/2009
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
Ordering Information
Part Number
NT1GT72U89D0BV-3C
NT2GT72U4PD0BV-3C
NT2GT72U8PD0BV-3C
NT4GT72U4ND0BV-3C
NT1GT72U89D0BV-AD
NT2GT72U4PD0BV-AD
NT2GT72U8PD0BV-AD
NT4GT72U4ND0BV-AD
400MHz (2.5ns @ CL = 6)
DDR2-800
PC2-6400
333MHz (3ns @ CL = 5)
DDR2-667
PC2-5300
Speed
Organization
128Mx72
256Mx72
256Mx72
512Mx72
128Mx72
256Mx72
256Mx72
512Mx72
Gold
1.8V
Leads
Power
Pin Description
Pin Name
CK0
CKE[1:0]
Description
Clock Input, positive line
Clock input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
[1:0]
A[9:0], A[13:11]
A10/AP
BA[2:0]
SCL
SDA
SA[2:0]
Par_In
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Addresses
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Address and Control bus
Register and PLL control pin
Pin Name
ODT[1:0]
DQ[63:0]
CB[7:0]
DQS[8:0]
[8:0]
[17:9]
RFU
NC
TEST
V
DDSPD
V
SS
V
DD
V
DDQ
V
REF
Description
On Die Termination Inputs
Data input/output
Data Check Bit Input/Output
Data strobes
Data strobes / negative line
Data strobes / negative line
Reserved for Future use
No Connect
Memory bus test tool
Serial EEPROM positive power supply
Ground
Core Power
I/O Power
Input/Output Reference
DM[8:0] / DQS[17:9] Data Masks / Data strobes
REV 1.1
01/2009
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
DDR3 SDRAM Pin Assignment
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
DQS3
Vss
DQ26
DQ27
Vss
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
Vss
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
V
DDQ
NC,
NC, ODT1
V
DDQ
Vss
DQ32
DQ33
DQS1
V
SS
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
Front
V
REF
V
SS
DQ0
DQ1
V
SS
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
KEY
V
SS
V
SS
V
DD
Par_In
V
DD
A10/AP
BA0
V
DDQ
V
DDQ
A11
A7
V
DD
A5
A4
V
DDQ
A2
V
DD
DQS8
V
SS
CB2
CB3
V
SS
V
DDQ
CKE0
V
DD
BA2
Front
CB0
CB1
V
SS
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
Front
V
SS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Back
V
SS
DQ4
DQ5
V
SS
DM0 / DQS9
NC,
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/DQS10
NC,
V
SS
RFU
RFU
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/DQS11
NC,
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DM3/DQS12
NC,
V
SS
DQ30
DQ31
V
SS
CB4
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
V
DDQ
ODT0
A13
V
DD
V
SS
DQ36
DQ37
V
SS
V
DD
A0
V
DD
BA1
V
DDQ
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
KEY
CK0
Back
CB5
V
SS
DM8/DQS17
NC,
V
SS
CB6
CB7
V
SS
V
DDQ
NC,CKE1
V
DD
NC
NC
V
DDQ
A12
A9
V
DD
A8
A6
V
DDQ
A3
A1
V
DD
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM4/DQS13
NC,
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5/DQS14
NC,
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
SS
DM6/DQS15
NC,
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/DQS16
NC,
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA0
SA1
Note: NC = No Connect; RFU = Reserved Future Use
ODT1, CKE1,
= for4GB module uses only
DQS9~DQS17 &
~
= for 2GB/4GB modules use only
REV 1.1
01/2009
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
Input/Output Functional Description
Symbol
CK0
0
Type
IN
IN
Polarity
Function
Positive Positive line of the differential pair of system clock inputs that drives input to the
Edge on-DIMM PLL.
Negative Negative line of the differential pair of system clock inputs that drives the input to the
Edge on-DIMM PLL.
Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder
when high. When decoder is disabled, new commands are ignored and previous
operations continue. These input signals also disable all outputs (except CKE and ODT)
of the register(s) on the DIMM when both inputs are high. When both “ [0:1] are high, all
register outputs (except CKE, ODT and Chip select) remain in the previous state. For
modules supporting 4 ranks, “ [2:3] operate similarly to “ [0:1] for a second set of
register outputs.
When sampled at the positive rising edge of the clock,
operation to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
Isolated power supply for the DDR2 SDRAM output buffers to provide improved noise
immunity
Active
High
-
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In
addition to the column address, AP is used to invoke autoprecharge operation at the end
of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1,
BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
Precharge command cycle, AP is used in conjunction with BA0, BA1,BA2 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define
which bank to precharge.
Data and Check Bit Input/Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
CKE[1:0]
IN
[1:0]
IN
Active
Low
,
V
REF
,
IN
Supply
Supply
IN
IN
Active
Low
,
,
define the
V
DDQ
ODT[1:0]
BA[2:0]
A[13:11,10/AP,9:0]
IN
-
DQ[63:0]
CB[7:0]
V
DD,
V
SS
DQS[17:0]
[17:0]
DM[8:0]
I/O
Supply
I/O
I/O
I/O
IN
-
-
Positive
Data strobe for input and output data
Edge
Negative
Data strobe for input and output data
Edge
Active
High
Active
Low
-
-
-
-
-
-
Masks write data when high, issued concurrently with input data.
The
pin is connected to the
pin on the register and to the OE pin on the PLL.
When low, all register outputs will be driven low and the PLL clocks to the DRAMs and
register(s) will be nset to low level (the PLL will remain synchronized with the input clock)
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply (wired to a separate power pin at the connector
which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt and 3.3 Volt)
operation.
Parity bit for the Address and Control bus. (1 for Odd, 0 for Even)
Parity error found in the Address and Control bus.
SA[2:0]
SDA
SCL
V
DDSPD
Par_In
IN
I/O
IN
Supply
IN
OUT
REV 1.1
01/2009
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GT72U89D0BV / NT2GT72U4PD0BV / NT4GT72U4ND0BV
NT2GT72U8PD0BV
1GB: 128M x 72 / 2GB: 256M x 72 / 4GB: 512M x 72
PC2-5300 / PC3-6400
Registered DDR2 SDRAM DIMM
Functional Block Diagram: Raw Card Version F
[1GB, 1Rank, 128Mx8 DDR2 SDRAMs]
REV 1.1
01/2009
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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