DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7214xxx
Module Configuration
VMS Part Number
VR5Vx287214EBP
VR5Vx287214EBS
VR5Vx287214EBW
VR5Vx287214EBZ
VR5Vx287214EBY
VR5Vx567214FBP
VR5Vx567214FBS
VR5Vx567214FBW
VR5Vx567214FBZ
VR5Vx567214FBY
VR5Vx567214ECP
VR5Vx567214ECS
VR5Vx567214ECW
VR5Vx127214FEP
VR5Vx127214FES
VR5Vx127214FEW
VR5Vx127214GBP
VR5Vx127214GBS
VR5Vx127214GBW
VR5Vx127214GBZ
VR5Vx127214GBY
VR5Vx127214FCP
VR5Vx127214FCS
VR5Vx127214FCW
VR5Vx127214EPP
VR5Vx127214EPS
VR5Vx1G7214FPP
VR5Vx1G7214FPS
Notes:
VA = Address Parity
VR = No Address Parity
Capacity
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
4GB
8GB
8GB
Module
Device
Configuration
Configuration
128Mx72
128M x 4 bit (18)
128Mx72
128M x 4 bit (18)
128Mx72
128M x 4 bit (18)
128Mx72
128M x 4 bit (18)
128Mx72
128M x 4 bit (18)
256Mx72
256M x 4 bit (18)
256Mx72
256M x 4 bit (18)
256Mx72
256M x 4 bit (18)
256Mx72
256M x 4 bit (18)
256Mx72
256M x 4 bit (18)
256Mx72
128M x 4 bit (36)
256Mx72
128M x 4 bit (36)
256Mx72
128M x 4 bit (36)
512Mx72
256M x 4 bit (36 die)
512Mx72
256M x 4 bit (36 die)
512Mx72
256M x 4 bit (36 die)
512Mx72
512M x 4 bit (18)
512Mx72
512M x 4 bit (18)
512Mx72
512M x 4 bit (18)
512Mx72
512M x 4 bit (18)
512Mx72
512M x 4 bit (18)
512Mx72
256M x 4 bit (36)
512Mx72
256M x 4 bit (36)
512Mx72
256M x 4 bit (36)
512Mx72
128M x 4 bit (72)
512Mx72
128M x 4 bit (72)
1Gx72
256M x 4 bit (72)
1Gx72
256M x 4 bit (72)
Device
Package
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
RAM-Stack™
RAM-Stack™
RAM-Stack™
DDP BGA
DDP BGA
DDP BGA
FBGA
FBGA
FBGA
FBGA
FBGA
RAM-Stack™
RAM-Stack™
RAM-Stack™
RAM-Stack™
RAM-Stack™
RAM-Stack™
RAM-Stack™
Module
Performance
Ranks
1
PC2-3200
1
PC2-4200
1
PC2-5300
1
PC2-6400
1
PC2-6400
1
PC2-3200
1
PC2-4200
1
PC2-5300
1
PC2-6400
1
PC2-6400
2
PC2-3200
2
PC2-4200
2
PC2-5300
2
PC2-3200
2
PC2-4200
2
PC2-5300
1
PC2-3200
1
PC2-4200
1
PC2-5300
1
PC2-6400
1
PC2-6400
2
PC2-3200
2
PC2-4200
2
PC2-5300
4
PC2-3200
4
PC2-4200
4
PC2-3200
4
PC2-4200
CAS
Latency
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL6 (6-6-6)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL5 (5-5-5)
CL3 (3-3-3)
CL4 (4-4-4)
CL3 (3-3-3)
CL4 (4-4-4)
Features
•
•
•
•
•
•
•
•
•
•
•
•
Single 1.8V
±
0.1V Power Supply
Registered inputs with one-clock delay
CAS Latency: CL 3, 4, 5
Burst Length (4, 8)
Burst type (Sequential & Interleave)
Auto & Self-Refresh.
8k/64ms Refresh Period.
Differential CLK (/CLK) input.
On-die termination (ODT)
Off-chip driver (OCD) impedance calibration
Serial Presence Detect with EEPROM.
RoHS Compliant* (see last page)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette
Page 1 of 19
DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7214xxx
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
/CK0
CKE [1:0]
TYPE
IN
IN
IN
POLARITY
Positive Edge
Negative Edge
Active High
DESCRIPTION
Positive line of the differential pair of system clock inputs that drives input to the
on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input
to the on-DIMM PLL.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers of the SDRAMs. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables
decoder when high. When decoder is disabled, new commands are ignored and
previous operations continue. These input signals also disable all outputs
(except CKE and ODT) of the register(s) on the DIMM when both inputs are
high. When both /S[0:1] are high, all register outputs (except CKE, ODT and
Chip select) remain in the previous state. For modules supporting 4 ranks,
/S[2:3] operate similarly to /S[0:1] for a second set of register outputs.
On-Die Termination control signals
CAS, WE When sampled at the positive rising edge of the clock, /CAS, /RAS,
and /WE define the operation to be executed by the SDRAM.
Reference voltage for SSTL18 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved
noise immunity
Selects which SDRAM bank of four or eight is activated.
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address.
In addition to the column address, AP is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If AP is high, autoprecharge
is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in
conjunction with BA0, BA1, and BA2 to control which bank(s) to precharge. If
AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or
BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to
precharge.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD to
configure the serial SPD EEPROM address range.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from the SDA bus line to VDDSPD on the system
planar to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected from the SCL bus time to VDDSPD on the system planar to
act as a pull-up.
/S [3:0]
IN
Active Low
ODT[1:0]
/RAS, /CAS, /WE
VREF
VDD
BA [2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A [n:0]
IN
-
DQ [63:0],
CB [7:0]
VDD, VSS
DQS [17:0]
/DQS [17:0]
SA [2:0]
SDA
SCL
I/O
Supply
I/O
I/O
IN
I/O
IN
-
-
Positive Edge
Negative Edge
-
-
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette
Page 3 of 19
DDR2 PC2-xx00
ECC REGISTERED VLP DIMM
VR5Vxxx7214xxx
PIN FUNCTION DESCRIPTION
SYMBOL
VDDSPD
TYPE
Supply
POLARITY
-
DESCRIPTION
Serial EEPROM positive power supply (wired to a separate power pin at the
connector which supports from 1.7 Volt to 3.6 Volt (nominal 1.8 Volt, 2.5 Volt
and 3.3 Volt) operations.
The RESET pin is connected to the RST pin on the register and to the OE pin
on the PLL. When low, all register outputs will be driven low and the PLL clocks
to the DRAMs and register(s) will be set to low level (the PLL will remain
synchronized with the input clock)
/RESET
Par_In
Err_Out
IN
IN
OUT
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Parity error found in the Address and Control bus
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS5Vxxx7214xxx Revision D Created By: Brian Ouellette
Page 4 of 19
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