NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
64Mx72 bit One Bank Registered SDRAM Module
based on 64Mx4, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
Features
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JEDEC-standard 168-pin, dual in-line memory module
(DIMM)
PC133- and PC100-compliant
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
ECC-optimized pinout
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V
±
0.3V Power Supply
Fully synchronous to positive edge
Suspend Mode and Power Down Mode
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge commands
SDRAMs have 4 internal banks (64Mx4 SDRAM)
Module has 1 physical bank 512MB (64 Meg x 72)
8192 Refresh cycles distributed across 64ms
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DIMM
CAS
latency * (Registered mode) :
Speed grade
-7K
-75B
-8B
Frequency
133MHz
133MHz
100MHz
CAS
latency
3
4
3
* DIMM
CAS
latency = device CL + 1 for registered mode.
Programmable Operation:
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, and 8
- Operation: Burst Read and Write or Multiple Burst Read with
Single Write
Gold contacts
SDRAMs in TSOP Type II Package
Serial Presence Detect (SPD) with Write Protect
Description
The NANYA NT512S72V4PA0GR is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module (DIMM) organized as a 64Mx72
high-speed memory array. The DIMM uses eighteen 64Mx4 SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed
data-transfer rates of 100MHz and 133MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system
clock.
The DIMM is intended for use in applications operating at 100MHz and 133MHz memory bus speeds. All control and address signals are
re-driven through registers/buffers to the SDRAM devices. Operating in registered mode (REGE pin tied high), the control/address input signals
are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed
by one clock).
A phase-lock loop (PLL) on the DIMM is used to re-drive the clock signals to both the SDRAM devices and the registers to minimize system
clock loading. (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated on the DIMM). A single clock enable (CKE0) controls all
devices on the DIMM, enabling the use of SDRAM Power Down modes.
Prior to any access operation, the device
CAS
latency and burst type/length/operation type must be programmed into the DIMM by address
inputs A0-A12 and I/O addresses BA0 and BA1 using the mode register set cycle. The DIMM
CAS
latency when operated in Registered mode
is one clock later than the device
CAS
latency due to the address and control signals being clocked to the SDRAM devices.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data
are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by
providing a high level to pin 81 on the DIMM. An on-board pull-down resistor keeps this in the Write Enable mode.
All NANYA 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.
Ordering Information
Device Timing
Part Number
MHz.
143MHz
NT512S72V4PA0GR -7K
133MHz
133MHz
NT512S72V4PA0GR -75B
100MHz
125MHz
NT512S72V4PA0GR -8B
100MHz
* CL = CAS Latency
2
2
2
3
2
3
2
3
2
3
3
4
2
3
2
3
2
3
3
4
64Mx72
Gold
3.3V
CL
3
t RCD
3
t RP
3
4
DIMM
CAS
latency
Organization
Leads
Power
Preliminary
06 / 2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
Pin Description
CK0 – CK3
CKE0
Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-precharge
SDRAM Bank Address Inputs
Data input/output
CB0-CB7
DQMB0-DQMB7
V
DD
V
SS
NC
SCL
SDA
SA0-2
WP
REGE
Check Bit Data input/output
Data Mask
Power (3.3V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial Presence Detect Write Protect Input
Register Enable
RAS
CAS
WE
S0
,
S2
A0-A9, A11, A12
A10 / AP
BA0, BA1
DQ0-DQ63
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQMB1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQMB5
NC
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
V
DD
DQ20
NC
NC
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
DD
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CK3
NC
SA0
SA1
SA2
V
DD
S0
NC
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CK0
V
SS
NC
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CK1
A12
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
S2
DQMB2
DQMB3
NC
V
DD
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
WE
DQMB0
CAS
DQMB4
Preliminary
06 / 2001
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
Block Diagram
(1 Bank, 64Mx4 SDRAMs)
RS0
RDQMB0
DQ0
DQ1
DQ2
DQ3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
CS
D0
DQ32
DQ33
DQ34
DQ35
RDQMB4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQ40
DQ41
DQ42
DQ43
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
CS
D9
CS
D1
DQ36
DQ37
DQ38
DQ39
RDQMB5
CS
D10
DQ4
DQ5
DQ6
DQ7
RDQMB1
CS
D2
CS
D11
CS
D3
CS
D12
CS
D4
CB4
CB5
CB6
CB7
CS
D13
CB0
CB1
CB2
CB3
RS2
RDQMB2
DQ16
DQ17
DQ18
DQ19
RDQMB6
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
CS
D5
DQ48
DQ49
DQ50
DQ51
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQ52
DQ53
DQ54
DQ55
RDQMB7
DQ56
DQ57
DQ58
DQ59
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
CS
D14
CS
D6
CS
D15
DQ20
DQ21
DQ22
DQ23
RDQMB3
DQ24
DQ25
DQ26
DQ27
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
CS
D7
CS
D16
CS
D8
DQ60
DQ61
DQ62
DQ63
CS
D17
DQ28
DQ29
DQ30
DQ31
Serial PD
S0 / S2
DQMB0-DQMB7
BA0-BA1
A0 - A12
RAS
CAS
CKE0
WE
10K
VDD
REGE
PCK
Notes :
R
E
G
I
S
T
E
R
RS0 / RS2
RDQMB0-RDQMB7
RBA0-RBA1
BA0-BA1 : SDRAMs D0 - D17
RA0-RA12
A0 - A12 : SDRAMs D0 - D17
RRAS
RAS : SDRAMs D0- D17
RCAS
CAS : SDRAMs D0- D17
RCKE0
CKE : SDRAMs D0- D17
RWE
WE : SDRAMs D0- D17
SCL
WP A0
SA0
V
DD
V
SS
CK0
PLL
12pF
CK1 - CK3
12pF
1. All resistor values are 10 ohms unless otherwise specified.
A1
SA1
A2
SA2
D0 - D17
D0 - D17
D0-D17
SDA
Preliminary
06 / 2001
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
Input/Output Functional Description
Symbol
CK0 - CK3
Type
Input
Polarity
Positive
Edge
Active
CKE0
Input
High
Active
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
their associated clock. CK0 drives the PLL. CK1, CK2 andCK3 are terminated.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
Enables the associated SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but previous
Low
Active
operations continue.
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the operation to be
executed by the SDRAM.
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
A0 - A9
A10/AP
A11, A12
Input
-
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9,A11)
when sampled at the rising clock edge. In addition to the column address, AP is used to invoke
Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is
selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which
bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of
BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63,
CB0 - CB7
Input
-
/Output
The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high
Active
DQMB0 -DQMB7
Input
High
impedance state when sampled high. In Read mode, DQMB has a latency of three clock cycles in
Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB
has a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high.
Active
High
REGE
Input
(Register
Mode
Enable)
SA0 – SA2
Input
Input
SDA
/Output
SCL
Input
-
Active
WP
Input
High
V
DD
, V
SS
Supply
-
-
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the Serial
Presence Detect EEPROM address.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus time to V
DD
to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to V
DD
to act as a pull up.
This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the SPD
EEPROM.
Power and ground for the module.
The Register Enable pin must be held high for proper registered mode operation (signals re-driven
to the SDRAMs when the clock rises, and held valid until the next rising clock).
Data and Check Bit input/output pins .
S0
,
S2
Input
RAS
,
CAS
,
WE
BA0, BA1
Input
Low
Input
-
Preliminary
06 / 2001
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512S72V4PA0GR
512MB : 64M x 72
Registered SDRAM Module
Absolute Maximum Ratings
Symbol
V
DD
V
IN
V
OUT
T
A
T
STG
P
D
I
OUT
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
Short Circuit Output Current
Rating
-0.3 to +4.6
-1.0 to 4.6
-1.0 to 4.6
0 to +70
-55 to +125
10.3
50
V
1
Units
Notes
°C
°C
W
mA
1
1
1,2
1
1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Maximum power is calculated assuming the DIMM is Auto Refresh mode.
Recommended DC Operating Conditions
(T
A
=0 to 70
°C)
Rating
Symbol
V
DD
V
IH
V
IL
V
OH
V
OL
I
IL
1.
2.
3.
Power Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage current
Parameter
Min.
3.0
2.0
-0.3
2.4
-
-10
Typ.
3.3
-
-
-
-
-
Max.
3.6
V
DD
+ 0.3
0.8
-
0.4
10
V
V
V
V
V
uA
1
1,2
1,3
Units
Notes
All voltages referenced to V
SS
.
V
IH
(max) = V
DD
/ V
DDQ
+ 1.2V for pulse width
≤
5ns
V
IL
(min) = V
SS
/ V
SSQ
- 1.2V for pulse width
≤
5ns .
Capacitance
(T
A
=25
°C
, f =1MHz, V
DD
=3.3 ± 0.3V)
Symbol
C
I1
C
I2
C
I3
C
I4
C
I5
C
I6
C
I7
C
IO1
C
IO2
Parameter
Input Capacitance (A0-A9, A10/AP, A11, A12, BA0, BA1, CKE0,
RAS
,
CAS
,
WE
)
Input Capacitance (
S0
-
S2
)
Input Capacitance (DQMB0 - DQMB7)
Input Capacitance (REGE)
Input Capacitance (CK0)
Input Capacitance (CK1, CK2, CK3)
Input Capacitance (SA0 - SA2, SCL, WP)
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
Input/Output Capacitance (SDA)
Max.
19
15
14
10
28
24
9
13
11
pF
Unit
Preliminary
06 / 2001
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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