NT512T72U89A5BD
/
NT512T72U89A2BN
/ NT512T72U89A0BE
NT1GT72U8PA3BD
/
NT1GT72U8PA2BN
/ NT1GT72U8PA0BE
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
Preliminary
240pin DDR2 SDRAM Fully Buffered DIMM
Based on 64Mx8 & 128Mx4 DDR2 SDRAM
Features
• 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8
DDR2 SDRAM (NT5TU64M8AE).
• 1GB 128Mx72 DDR2 Fully Buffered DIMM based on 64Mx8
DDR2 SDRAM (NT5TU64M8AE).
• 2GB 256Mx72 DDR2 Fully Buffered DIMM based on 128Mx4
DDR2 SDRAM (NT5TU128M4AE).
• JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line
Memory Module.
• Performance:
PC2-4200
Speed Sort
DIMM
Latency
*
f
CK
t
CK
f
DQ
Clock
Frequency
Clock
Cycle
DQ Burst
Frequency
-4B
4
266
3.75
533
PC2-5300
-3C
5
333
3
667
MHz
ns
MHz
Unit
• Intended for 266MHz and 333MHz applications.
• Inputs and outputs are SSTL-18 compatible.
• V
DD
= 1.8Volt ± 0.1, V
DDQ
= 1.8Volt ± 0.1.
• Host Interface and AMB component industry standard
compliant.
• Support SMBus protocol interface for access to the AMB
configuration registers.
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• MBIST & IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Serial Presence Detect (SPD)
• Gold contacts
• RoHS Compliant products
• SDRAMs in 60-ball FBGA Package
Description
NT512T72U89A5BD, NT512T72U89A2BN, NT512T72U89A0BE, NT1GT72U8PA3BD, NT1GT72U8PA2BN, NT1GT72U8PA0BE,
NT2GT72U4NA1BD, and NT2GT72U4NA1BN are Fully Buffered 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Dual In-Line
Memory Module (DIMM), organized as one bank 64Mx72 & 128Mx72 and two bank 256Mx72 high-speed memory array. The module
uses nine 64Mx8 (512MB), eighteen 64Mx8 (1GB), and thirty-six 128Mx4 (2GB) DDR2 SDRAMs in FBGA packages. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25”
long space-saving footprint.
The DIMM is intended for use in applications operating up to 333MHz clock speeds and achieves high-speed data transfer rates of up to
667 MHz. Prior to any access operation, the device
latency and burst type/length/operation type must be programmed into the
DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
REV 0.6
02/27/2006
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A5BD
/
NT512T72U89A2BN
/ NT512T72U89A0BE
NT1GT72U8PA3BD
/
NT1GT72U8PA2BN
/ NT1GT72U8PA0BE
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
Preliminary
Ordering Information
Part Number
NT512T72U89A5BD-4B
NT512T72U89A2BN-4B
NT512T72U89A0BE-4B
NT1GT72U8PA3BD-4B
NT1GT72U8PA2BN-4B
NT1GT72U8PA0BE-4B
NT2GT72U4NA1BD-4B
NT2GT72U4NA1BN-4B
NT512T72U89A5BD-3C
NT512T72U89A2BN-3C
NT512T72U89A0BE-3C
NT1GT72U8PA3BD-3C
NT1GT72U8PA2BN-3C
NT1GT72U8PA0BE-3C
NT2GT72U4NA1BD-3C
NT2GT72U4NA1BN-3C
AMB
IDT
INTEL
NEC
IDT
INTEL
NEC
IDT
INTEL
IDT
INTEL
NEC
IDT
INTEL
NEC
IDT
INTEL
256Mx72
333MHz
(3ns @ CL = 5)
DDR2-667
PC2-5300
64Mx72
256Mx72
Gold
1.8V
266MHz
(2.75ns @ CL = 4)
DDR2-533
PC2-4200
64Mx72
Speed
Organization
Leads
Power
128Mx72
128Mx72
Note:
FBDIMM module revision will change if AMB, PCB, or Heat spreader version changes.
Ex:
REV 0.6
02/27/2006
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A5BD
/
NT512T72U89A2BN
/ NT512T72U89A0BE
NT1GT72U8PA3BD
/
NT1GT72U8PA2BN
/ NT1GT72U8PA0BE
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
Preliminary
DIMM Connector Pin Description
Pin Name
SCK
PN0-PN13
-
PS0-PS9
-
SN0-SN13
-
SS0-SS9
-
SCL
SDA
SA0-SA2
VID0-VID1
Pin Description
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address Inputs, also used to select the DIMM number in the AMB
Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID0 is V
DD
value: OPEN=1.8V, GND=1.5V; VID1 is V
CC
value: OPEN=1.5V, GND=1.2V
AMB reset signal
RFU
V
CC
V
DD
V
TT
V
DDSPD
V
SS
Reserved for Future Use
AMB Core Power and AMB Channel Interface Power (1.5V)
DRAM Power and AMB DRAM I/O Power (1.8V)
DRAM Address/Command/Clock Termination Power (V
DD
/2)
SPD Power (3.3V)
Ground
It provides an external connection on R/Cs A-D for testing the margin of Vref which is
produced by a voltage divider on the module. It is not intended to be used in normal
system operation and must not be connected (DNU) in a system. This test pin may have
other features on future card designs and if it does, will be included in this specification at
that time.
2
Note
1
1
DNU/M_TEST
1
Note:
1.
2.
System Clock Signals SCK and SCK switch at one half the DRAM CK/
frequency
Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
REV 0.6
02/27/2006
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A5BD
/
NT512T72U89A2BN
/ NT512T72U89A0BE
NT1GT72U8PA3BD
/
NT1GT72U8PA2BN
/ NT1GT72U8PA0BE
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
Preliminary
DDR2 240-pin FBDIMM Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
V
SS
PN13
V
SS
PN5
V
SS
PN4
V
SS
PN3
V
SS
PN2
69
70
71
72
73
74
75
76
77
78
79
80
81
V
SS
V
SS
PS3
V
SS
PS2
V
SS
PS1
V
SS
PN1
V
SS
RFU**
RFU**
V
SS
PN0
Front Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID1
Pin
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
V
SS
KEY
V
SS
PS0
V
SS
PN11
V
SS
PN10
V
SS
PN9
V
SS
PN8
V
SS
PN7
V
SS
PN6
Front Side
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
PN12
Pin
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
V
SS
RFU**
RFU**
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
SA2
SDA
SCL
V
SS
PS8
V
SS
PS7
V
SS
PS6
V
SS
PS5
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
PS9
Front Side
PS4
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
SN13
V
SS
SN5
V
SS
SN4
V
SS
SN3
V
SS
SN2
189
190
191
192
193
194
195
196
197
198
199
200
201
V
SS
V
SS
SS3
V
SS
SS2
V
SS
SS1
V
SS
SN1
Back Side
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID0
DNU/M_TEST
V
SS
RFU**
RFU**
V
SS
SN0
Pin
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
V
SS
KEY
V
SS
SS0
V
SS
SN11
V
SS
SN10
V
SS
SN9
V
SS
SN8
V
SS
SN7
V
SS
SN6
Back Side
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
SN12
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
V
DDSPD
SA0
SA1
V
SS
RFU**
RFU**
V
SS
SCK
V
SS
SS8
V
SS
SS7
V
SS
SS6
V
SS
SS5
V
SS
V
SS
RFU*
RFU*
V
SS
V
SS
SS9
Back Side
SS4
Note:
RFU = Reserved Future Use
* These pin positions are reserved for forwarded clocks to be used in future module implementation
** These pin positions are reserved for future architecture flexibility
The following signals are CRC bits and thus appear out of the normal sequence: PN12/
, SN12/
PS9/
, SS9/
, PN13/
, SN13/
,
REV 0.6
02/27/2006
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512T72U89A5BD
/
NT512T72U89A2BN
/ NT512T72U89A0BE
NT1GT72U8PA3BD
/
NT1GT72U8PA2BN
/ NT1GT72U8PA0BE
NT2GT72U4NA1BD / NT2GT72U4NA1BN
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
Preliminary
Functional Block Diagram
(Raw Card Version A, 512MB, 1Rank, 64Mx8 DDR2 SDRAMs)
REV 0.6
02/27/2006
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
