M1N25664TUH4A2F / M1N51264TUH8A2F
256MB: 32M x 64 / 512MB: 64M x 64
PC2-5300 Unbuffered DDR2 SO-DIMM
200 pin Unbuffered DDR2 SO-DIMM
Based on DDR2-667 32Mx16 SDRAM
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 32Mx64 and 64Mx64 Unbuffered DDR2 SO-DIMM based on
32Mx16 DDR2 SDRAM devices.
• Performance:
PC2-5300
Speed Sort
DIMM
CAS
Latency
f
CK
t
CK
f
DQ
3C
5
333
3
667
MHz
ns
MHz
Unit
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 3, 4, 5
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/1 Addressing (M1N25664TUH4A2F)
13/10/2 Addressing (M1N51264TUH8A2F)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 84-ball FBGA Package
• Intended for 333MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
DD
= V
DDQ
= 1.8V ± 0.1V
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
Description
M1N25664TUH4A2F and M1N51264TUH8A2F are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-
Line Memory Module (SO-DIMM), organized as one rank of 32x64 and two ranks of 64x64 high-speed memory array. Modules use four 32Mx16
(M1N25664TUH4A2F) or eight 32Mx16 (M1N51264TUH8A2F) 84-ball FBGA packaged devices. These DIMMs are manufactured using raw
cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between
suppliers. All Super Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.
The DIMM is intended for use in applications operating up to 333 MHz clock speeds and achieves high-speed data transfer rates of up to
667MHz . Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.0
06/14/2005
1
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M1N25664TUH4A2F / M1N51264TUH8A2F
256MB: 32M x 64 / 512MB: 64M x 64
PC2-5300 Unbuffered DDR2 SO-DIMM
Ordering Information
Part Number
M1N25664TUH4A2F– 3C
M1N51264TUH8A2F– 3C
Speed
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
DDR2-667 PC2-5300 333MHz (3ns @ CL = 5)
Organization
32Mx64
64Mx64
Power
1.8V
Gold
Green
Leads
Note
Green
REV 1.0
06/14/2005
2
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M1N25664TUH4A2F / M1N51264TUH8A2F
256MB: 32M x 64 / 512MB: 64M x 64
PC2-5300 Unbuffered DDR2 SO-DIMM
Pin Description
CK0,
CK0
CKE0, CKE1
RAS
CAS
WE
CS0, CS1
A0-A12
A0-A9
A10/AP
BA0, BA1
ODT0, ODT1
NC
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Row Address Inputs
Column Address Inputs
Column Address Input/Auto-precharge
SDRAM Bank Address Inputs
Active termination control lines
No Connect
DQ0-DQ63
DQS0-DQS7
DQS0-DQS7
DM0-DM7
V
DD
V
REF
V
DDSPD
V
SS
SCL
SDA
SA0, SA1
Data input/output
Bidirectional data strobes
Differential data strobes
Input Data Masks
Power (1.8V)
Ref. Voltage for SSTL_18 inputs
Serial EEPROM positive power supply
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2
Pin Back
2
4
6
8
V
SS
DQ4
DQ5
V
SS
Pin Front
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
(BA2)
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Back
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3
DQS3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
(A15)
(A14)
V
DD
A11
A7
A6
V
DD
A4
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Front
A1
V
DD
A10/AP
BA0
WE
V
DD
CAS
CS1
V
DD
ODT1
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
A0
V
DD
BA1
RAS
CS0
V
DD
ODT0
(A13)
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5
DQS5
V
SS
Pin Front
151 DQ42
153 DQ43
155 V
SS
157 DQ48
159 DQ49
161 V
SS
163 NC
165 V
SS
167
DQS6
169 DQS6
171 V
SS
173 DQ50
175 DQ51
177 V
SS
179 DQ56
181 DQ57
183 V
SS
185 DM7
187 V
SS
189 DQ58
191 DQ59
193 V
SS
195 SDA
197 SCL
199 V
DDSPD
Pin Back
152 DQ46
154 DQ47
156 V
SS
158 DQ52
160 DQ53
162 V
SS
164 CK1
166
CK1
168 V
SS
170 DM6
172 V
SS
174 DQ54
176 DQ55
178 V
SS
180 DQ60
182 DQ61
184 V
SS
186
DQS7
188 DQS7
190 V
SS
192 DQ62
194 DQ63
196 V
SS
198 SA0
200 SA1
10 DM0
12 V
SS
14 DQ6
16 DQ7
18 V
SS
20 DQ12
22 DQ13
24 V
SS
26 DM1
28 V
SS
30 CK0
32
CK0
34 V
SS
36 DQ14
38 DQ15
40 V
SS
42 V
SS
44 DQ20
46 DQ21
48 V
SS
50 NC
100 A2
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.0
06/14/2005
3
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M1N25664TUH4A2F / M1N51264TUH8A2F
256MB: 32M x 64 / 512MB: 64M x 64
PC2-5300 Unbuffered DDR2 SO-DIMM
Input/Output Functional Description
Symbol
CK0
CK0
Type
(SSTL)
Polarity
Function
The positive line of the differential pair of system clock inputs which drives the input to
Positive
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
Edge
rising edge of their associated clocks.
Negative The negative line of the differential pair of system clock inputs which drives the input to
Edge the on-DIMM PLL.
Active
High
Active
Low
Active
Low
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
operation to be executed by the SDRAM.
Reference voltage for SSTL-18 inputs
Active
High
-
On-Die Termination control signals
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-
CA10) when sampled at the rising clock edge. In addition to the column address, AP is
used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If
AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If
AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-
charge.
Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM
configurations.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Data strobe for input and output data
Positive
Edge
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
(SSTL)
CKE0, CKE1
(SSTL)
CS0, CS1
RAS
,
CAS
,
WE
V
REF
ODT0, ODT1
BA0, BA1
(SSTL)
(SSTL)
Supply
Input
(SSTL)
A0 - A9
A10/AP
A11, A12
(SSTL)
-
DQ0 – DQ63
CB0 – CB7
V
DD
,
V
SS
DQS0 – DQS7
DQS0
–
DQS7
(SSTL)
Supply
Active
High
(SSTL)
DM0 – DM7
Input
SA0 – SA2
SDA
SCL
V
DDSPD
Supply
-
-
-
REV 1.0
06/14/2005
4
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
M1N25664TUH4A2F / M1N51264TUH8A2F
256MB: 32M x 64 / 512MB: 64M x 64
PC2-5300 Unbuffered DDR2 SO-DIMM
Functional Block Diagram
(256MB
–
1 Rank, 32Mx16 DDR2 SDRAMs)
CS0
CS
CS
DQS0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D0
DQS4
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D2
DQS2
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS CS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
D1
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS6
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS CS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
D3
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
BA0-BA1 : SDRAMs D0-D3
A0-A12 : SDRAMs D0-D3
RAS
: SDRAMs D0-D3
CAS
: SDRAMs D0-D3
CKE : SDRAMs D0-D3
N.C.
WE
: SDRAMs D0-D3
SCL
WP
V
DDSPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
SPD
D0-D3
D0-D3
D0-D3
CK0
CK0
CK1
CK1
2 loads
2 loads
Serial PD
A0
SA0
A1
SA1
A2
SA2
SDA
Notes :
1.
2.
3.
4.
DQ wiring may differ from that described in this drawing .
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.0
06/14/2005
5
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION
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