NT512D64S8HBAFM
512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM
200pin Unbuffered DDR SO-DIMM
Based on DDR333/266 32Mx8 SDRAM
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 64Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8
DDR SDRAM.
• Performance:
PC2700 PC2100
Speed Sort
DIMM
CAS
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
f
DQ
DQ Burst Frequency
-6K
2.5
166
6
333
-75B
2.5
133
7.5
266
MHz
ns
MHz
Unit
• DRAM DLL aligns DQ and DQS transitions with clock
transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/2 Addressing (row/column/bank)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 60-ball CSP Package
• Intended for 133 MHz and 166 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= 2.5Volt ± 0.2, V
DDQ
= 2.5Volt ± 0.2
• SDRAMs have 4 internal banks for concurrent operation
• Module has two physical banks
• Differential clock inputs
• Data is read or written on both clock edges
Description
NT512D64S8HBAFM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module
(SO-DIMM), organized as a two-bank 64Mx64 high-speed memory array. The module uses sixteen 32Mx8 DDR SDRAMs in 60-ball CSP
packages. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.
The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to
333 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
NT512D64S8HBAFM-6K
Speed
166MHz (6ns @ CL = 2.5)
133MHz (7.5ns @ CL = 2)
133MHz (7.5ns @ CL = 2.5)
100MHz (10ns @ CL = 2)
DDR333
PC2700
64Mx64
DDR266B
PC2100
Gold
2.5V
Organization
Leads
Power
NT512D64S8HBAFM-75B
REV 1.0
03/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512D64S8HBAFM
512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM
Pin Description
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0-A9, A11, A12
A10/AP
BA0, BA1
V
REF
V
DDID
Differential Clock Inputs.
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
DQ0-DQ63
DQS0-DQS7,
DQS9-DQS16
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bidirectional data strobes
Power (2.5V)
Supply voltage for DQs (2.5V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply (2.5V)
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
DD
DM2
DQ22
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Front
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
NC
NC
V
SS
DQS8
NC
V
DD
NC
DU
V
SS
CK2
CK2
V
DD
CKE1
DU
A12
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Back
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
NC
NC
V
SS
NC
NC
V
DD
NC
DU
V
SS
V
SS
V
DD
V
DD
CKE0
DU
A11
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Front
A9
V
SS
A7
A5
A3
A1
V
DD
A10/AP
V
DD
WE
S0
DU
V
SS
DQ32
DQ33
V
DD
DQS4
DQ34
V
SS
DQ35
DQ40
V
DD
DQ41
DQS5
V
SS
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS
CAS
S1
DU
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front
DQ42
DQ43
V
DD
V
DD
V
SS
V
SS
DQ48
DQ49
V
DD
DQS6
DQ50
V
SS
DQ51
DQ56
V
DD
DQ57
DQS7
V
SS
DQ58
DQ59
V
DD
SDA
SCL
V
DDSPD
V
DDID
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ46
DQ47
V
DD
CK1
CK1
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
DU
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.0
03/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512D64S8HBAFM
512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
Type
(SSTL)
Polarity
Cross
point
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point
of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read operations is synchronized to the
input clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
S0, S1
(SSTL)
Active
Low
Active
Low
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
RAS, CAS, WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
Supply
Supply
(SSTL)
-
When sampled at the positive rising edge of the clock,
RAS, CAS, WE
define the operation
to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
A0 - A9
A10/AP
A11, A12
when sampled at the rising clock edge. In addition to the column address, AP is used to
(SSTL)
-
invoke autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63
DQS0 - DQS7,
DQS9 – DQS16
V
DD,
V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
Supply
(SSTL)
(SSTL)
Supply
-
-
-
-
Active
High
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
(SSTL)
REV 1.0
03/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512D64S8HBAFM
512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM
Functional Block Diagram
(2 Bank, 32Mx8 DDR SDRAMs)
S1
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
Notes :
1.
2.
3.
4.
BA0-BA1 : SDRAMs D0-D15
A0-A12 : SDRAMs D0-D15
RAS
: SDRAMs D0-D15
CAS
: SDRAMs D0-D15
CKE : SDRAMs D0-D7
CKE : SDRAMs D8-D15
WE
: SDRAMs D0-D15
V
DDSPD
V
DD
/V
DDQ
VR
EF
V
SS
V
DDID
Serial PD
SCL
WP
A0
SA0
A1
SA1
SPD
D0-D15
D0-D15
D0-D15
Strap: see Note 4
A2
SA2
SDA
DQ-to-I/O wring may be changed within a byte.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22 Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.0
03/2003
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT512D64S8HBAFM
512MB : 64M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM
Serial Presence Detect --
Part 1 of 2
64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Byte
Description
DDR333
-6K
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=2.5
DDR SDRAM Device Access Time from Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
DDR SDRAM Device Attributes: Burst Length Supported
DDR SDRAM Device Attributes: Number of Device Banks
DDR SDRAM Device Attributes: CAS Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum Data
0.75ns
0.75ns
0.45ns
0.45ns
Initial
18ns
12ns
18ns
42ns
256MB
0.9ns
0.9ns
0.5ns
0.5ns
Initial
75
75
45
45
00
00
0B
00
C0
2/2.5
0
1
Differential Clock
+/-0.2V Voltage Tolerance
7.5ns
0.70ns
N/A
N/A
20ns
15ns
20ns
45ns
48
30
48
2A
40
90
90
50
50
10ns
0.75ns
75
70
00
00
50
3C
50
2D
6ns
0.7ns
128
256
SDRAM DDR
13
10
2
X64
X64
SSTL 2.5V
7.5ns
0.75ns
Non-Parity
SR/1x(7.8us)
X8
N/A
1 Clock
2,4,8
4
2/2.5
0C
01
02
20
00
A0
75
60
70
00
82
08
00
01
0E
04
0C
DDR266B
-75B
Serial PD Data Entry
(Hexadecimal)
DDR333
-6K
80
08
07
0D
0A
02
40
00
04
75
75
DDR266B
-75B
Note
Undefined
REV 1.0
03/2003
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
FPGA/CPLD
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