LT4948C(-G)
Dual N-Channel 60-V (D-S) MOSFET
GENERAL DESCRIPTION
The LT4948C is the Dual N-Channel logic enhancement mode power
field effect transistors, using high cell density, DMOS trench
technology. This high density process is especially tailored to
●
Exceptional on-resistance and maximum DC current
minimize on state resistance. These devices are particularly suited
for low voltage application such as cellular phone, notebook
computer power management and other battery powered circuits,
and low in-line power loss that are needed in a very small outline
surface mount package.
capability
FEATURES
●
R
DS(ON)
≦
53 mΩ@VGS=10V
●
R
DS(ON)
≦
78 mΩ@VGS=4.5V
●
Super high density cell design for extremely low R
DS(ON)
APPLICATIONS
●
Power Management in Note book
●
DC/DC Converter
●
Load Switch
●
LCD Display inverter
PIN CONFIGURATION
(SOP-8)
Top View
Ordering Information:
LT4948C (Pb-free)
LT4948C-G (Green product-Halogen free)
Absolute Maximum Ratings
(T
A
=25℃ Unless Otherwise Noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current(Tj=150℃)
Pulsed Drain Current
Single Pulse Avalanche Energy (L=0.1mH,I
AS
=8A)
T
A
=25℃
Maximum Power Dissipation
Operating Junction Temperature
Thermal Resistance-Junction to Ambient
*
The *
*
The device mounted on 1in FR4 board with 2 oz copper
2
Symbol
V
DSS
V
GSS
T
A
=25℃
T
A
=70℃
I
D
I
DM
E
AS
P
D
T
J
R
θJA
Rating
60
±20
4.5
3.6
18
3.2
1.67
1.07
-55 to 150
Steady State
75
Unit
V
V
A
A
mJ
W
℃
℃/W
T
A
=70℃
Rev 2. Nov. 2010
LT4948C(-G)
Dual N-Channel 60-V (D-S) MOSFET
Electrical Characteristics
(T
A
=25℃ Unless Otherwise Specified)
Symbol
STATIC
BV
DSS
V
GS(th)
I
GSS
I
DSS
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
V
GS
=0V, I
D
=250μA
V
DS
=V
GS
, I
D
=250μA
V
DS
=0V, V
GS
=±20V
V
DS
=60V, V
GS
=0V
V
DS
=60V, V
GS
=0V,T
J
=55℃
V
GS
=10V, I
D
= 4.5A
V
GS
=4.5V, I
D
= 3.6A
V
SD
DYNAMIC
Qg
Qg
Qgs
Qgd
C
iss
C
oss
C
rss
t
d(on)
tr
t
d(off)
t
f
Total Gate Charge
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
V
DD
=30V, R
L
=15Ω,
V
GEN
=10V, R
G
=1Ω
V
DS
=15V, V
GS
=0V,
f=1MHz
V
DS
=30V, V
GS
=4.5V, I
D
=4.5A
V
DS
=30V, V
GS
=10V, I
D
=4.5A
16
8.7
4.4
3.6
560
73
22
12
16
34
4
ns
pF
nC
Diode Forward Voltage
I
S
=2.0A, V
GS
=0V
45
60
0.8
60
1
3
±100
1
10
53
78
1.2
V
mΩ
V
V
nA
μA
Parameter
Limit
Min
Typ
Max
Unit
R
DS(ON)
Drain-Source On-Resistance
a
Notes: a. Pulse test: pulse width≦ 300us, duty cycle≦ 2%, Guaranteed by design, not subject to production testing.
Rev 2. Nov. 2010
LT4948C(-G)
Dual N-Channel 60-V (D-S) MOSFET
SOP-8 Package Outline
NOTES:
1. PKG ALL SURFACES ARE Ra0.8-1.2um.
2. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides).
Rev 2. Nov. 2010
嵌入式系统
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