LT4542
N- and P-Channel 30-V Power MOSFET
GENERAL DESCRIPTION
The LT4542 is the N- and P-Channel logic enhancement mode
power field effect transistors are produced using high cell density ,
DMOS trench technology. This high density process is especially
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage application such as cellular phone
and notebook computer power management and other battery
powered circuits where high-side switching, and low in-line power
loss are needed in a very small outline surface mount package.
FEATURES
●
R
DS(ON)
≦25mΩ@V
GS
=10V (N-Ch)
●
R
DS(ON)
≦40mΩ@V
GS
=4.5V (N-Ch)
●
R
DS(ON)
≦35mΩ@V
GS
=-10V (P-Ch)
●
R
DS(ON)
≦58mΩ@V
GS
=-4.5V (P-Ch)
●
Super high density cell design for extremely low R
DS(ON)
●
Exceptional on-resistance and maximum DC current
capability
APPLICATIONS
●
Power Management
●
DC/DC Converter
●
LCD TV & Monitor Display inverter
●
CCFL inverter
●
LCD Display inverter
PIN
CONFIGURATION
(SOP-8)
Top View
Absolute Maximum Ratings
(T
A
=25℃ Unless Otherwise Noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current(tJ=150℃)
Pulsed Drain Current
Maximum Power Dissipation
Operating Junction Temperature
Thermal Resistance-Junction to Ambient
*
Thermal Resistance-Junction to Case
*
*The device mounted on 1in2 FR4 board with 2 oz copper
N-Channel
Symbol
10 secs
Steady State
P-Channel
10 secs
Steady State
Unit
V
V
DSS
V
GSS
T
A
=25℃
T
A
=70℃
I
D
I
DM
T
A
=25℃
T
A
=70℃
P
D
T
J
R
θJA
R
θJC
48
2.6
1.67
8
6.4
30
±20
6.3
5
30
1.6
1
-55 to 150
78
50
46
2.7
1.7
-6.9
-5.5
-30
±20
-5.4
-4.3
-30
1.6
1
A
W
℃
77
48
℃/W
℃/W
Rev 0. Nov. 2007
Nov, 2007-Ver4.0
01
LT4542
N- and P-Channel 30-V Power MOSFET
Electrical Characteristics
(T
A
=25℃ Unless Otherwise Specified)
Symbol Parameter
STATIC
V
GS(th)
Gate Threshold Voltage
V
DS
=V
GS
, I
D
=250μA
V
DS
=V
GS
, I
D
=-250μA
V
DS
=0V, V
GS
=±20V
V
DS
=30V, V
GS
=0V
V
DS
=-30V, V
GS
=0V
I
DSS
Zero Gate Voltage Drain Current
V
DS
=30V, V
GS
=0V,T
J
=55℃
V
DS
=-30V, V
GS
=0V,T
J
=55℃
V
DS
≧5V,
V
GS
=
10V
V
DS
≦-5V,
V
GS
= -10V
V
GS
=10V, I
D
= 6.7A
V
GS
=-10V, I
D
= -6.1A
V
GS
=4.5V, I
D
= 5.0A
V
GS
=-4.5V, I
D
= -5.0A
I
S
=1.7A, V
GS
=0V
I
S
=-1.7A, V
GS
=0V
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
20
-20
21
30
32
48
0.8
-0.8
12
21
2
4
2.5
6
360
840
70
120
17
32
0.5
5.5
9.3
32
14
13
32
58
3.2
6.8
13
41
18
17
41
75
5
9
ns
Ω
420
980
pF
25
35
40
58
1.2
-1.2
15
25
nC
1.0
-1.0
1.5
-1.5
3.0
-3.0
±100
±100
1
-1
25
-25
μA
V
Conditions
Min
Typ
Max
Unit
I
GSS
Gate Leakage Current
nA
I
D(ON)
On-State Drain Current
a
A
R
DS(ON)
Drain-Source On-State Resistance
a
mΩ
V
SD
DYNAMIC
Qg
Qgs
Qgd
C
iss
C
oss
C
rss
Rg
Diode Forward Voltage
V
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
N-Channel
V
DS
=15V, V
GS
=10V, I
D
=6.7A
P-Channel
V
DS
=-15V, V
GS
=-10V, I
D
=-6.1A
N-Channel
V
DS
=15V, V
GS
=0V, f=1MHz
P-Channel
V
DS
=15V, V
GS
=0V, f=1MHz
V
DS
=0V, V
GS
=0V, f=1MHz
N-Channel
V
DD
=15V, R
L
=15Ω
I
D
=1A, V
GEN
=10V, R
G
=6Ω
P-Channel
V
DD
=-15V, R
L
=15Ω
I
D
=-1A, V
GEN
=-10V,R
G
=6Ω
t
d(on)
t
r
t
d(off)
t
f
Notes: a. Pulse test; pulse width
≦
300us, duty cycle≦ 2%
Rev 0. Nov. 2007
Nov, 2007-Ver4.0
02
嵌入式系统
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