SPT5507A
SP
Language Repeater
SEP. 21, 2001
Version 1.1
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO.
is believed to be accurate and reliable.
However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.
Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by
SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPT5507A
Table of Contents
PAGE
1. GENERAL DESCRIPTION ..........................................................................................................................................................................3
2. FEATURES ..................................................................................................................................................................................................3
3. BLOCK DIAGRAM ......................................................................................................................................................................................3
4. SIGNAL DESCRIPTIONS ............................................................................................................................................................................4
5. FUNCTIONAL DESCRIPTIONS ..................................................................................................................................................................5
5.1. C
LOCK
S
OURCE
S
ELECTION
...................................................................................................................................................................5
5.2. L
INEAR
B
LOCK
D
ESCRIPTION
..................................................................................................................................................................5
6. ELECTRICAL SPECIFICATIONS................................................................................................................................................................6
6.1. A
BSOLUTE
M
AXIMUM
R
ATINGS
................................................................................................................................................................6
6.2. DC C
HARACTERISTICS
(VDD = 5.0V; T
AMB
= 25℃, CPU
CLOCK
= 3.58MH
Z
) .........................................................................................6
7. APPLICATION CIRCUIT..............................................................................................................................................................................7
7.1. LCD L
ANGUAGE
R
EPEATER
A
PPLICATION
C
IRCUIT
..................................................................................................................................7
8. PACKAGE/PAD LOCATIONS .....................................................................................................................................................................8
8.1. PAD A
SSIGNMENT
..................................................................................................................................................................................8
8.2. O
RDERING
I
NFORMATION
........................................................................................................................................................................8
8.3. PAD L
OCATIONS
....................................................................................................................................................................................9
9. DISCLAIMER .............................................................................................................................................................................................10
10. REVISION HISTORY ................................................................................................................................................................................. 11
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© Sunplus Technology Co., Ltd.
Proprietary & Confidential
2
SEP. 21, 2001
Version: 1.1
SPT5507A
LANGUAGE REPEATER
1. GENERAL DESCRIPTION
The SPT5507A integrates an 8-bit CPU, speech generator,
segment LED driver, analog switches, programmable attenuator
and a gain amplifier into one chip.
The SPT5507A includes a
This chip which
40K-byte ROM, 128-byte working SRAM, 4 edge-mode interrupts
and a fixed time based generator (F
CPU
/1024)*.
incorporated with 1 or 2 pieces of 4M X 4 ARAM, can be applied to
the versatile audio field, such as a language repeater.
*F
CPU
: CPU clock
2. FEATURES
8-bit microprocessor
Provide 40K x 8 ROM area for program and audio data
128 x 8 working SRAM
Embedded LPF, ADC, DAC for analog processing
Provide controlled DRAM interfaces
4 Interrupt sources
Built in watch dog timer
3. BLOCK DIAGRAM
XI, XO
RESET
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ROSC. or Crystal OSC. selections
Provide low battery detector
Provide power down mode
CPU
MASK ROM
40K x 8
ARAM
INTERFACE
RAS, CAS1, CAS2, W, OE
A11 .... A0
D3 ... D0
KEY IN
LED DISPLAY
I/O PORT
BLOCK
KT8 ... KT1
EXTRA I/O
TEST
I/O DECODER
LINEO, AMPOUT, DACO,
AMPNF, SPO, DACO
HEAD, MIC
SRAM
128 x 8
ANALOG
BLOCK
LPFI, LPFO
LOW BATTERY
POWER FAIL
LBAT
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
3
SEP. 21, 2001
Version: 1.1
SPT5507A
4. SIGNAL DESCRIPTIONS
Mnemonic
XI
XO
OPT
PIN No.
44
45
46
Type
I
O
I
Description
Crystal OSC Input or ROSC tuning resistor, connected to AVDD
Crystal OSC Output
OSC type selector.
‘0’ or open for X’TAL, ‘1’ for ROSC
RESET
KT8 - 1
A2 - 0
A8 - 3
A11 - 9
D3 - 0
W
OE
RAS
CAS1
CAS2
DACO
LPFI
LPFO
LBAT
AMPOUT
SPO
AMPNF
VREF
MIC
HEAD
TEST
EXIO1
EXIO2
EXIO3
EXIO4
VDD
VSS
AVDD
AVSS
59
67 - 60
71 - 69
84 - 79
3-1
7-4
16
I
I/O
O
System reset, active low
LED segment driver, Open Drain NMOS output, and Key input (8- 1), TTL and CMOS
compatible Input.
ARAM Address A11 - 0
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I/O
O
ARAM Data D3 - 0
ARAM Write Enable
17
O
ARAM Output Enable
18
19
20
23
O
ARAM ROW Address Strobe
O
O
ARAM1 Column Address Strobe
ARAM2 Column Address Strobe
DAC Output
O
I
24
Low Pass Filter Input
25
O
I
Low Pass Filter Output
26
Low Battery detector Input
Gain Amplifier Output
27
37
O
O
I
Signal Output, goes to speaker amplifier
38
Gain Amplifier Input
39
O
I
Voltage Reference Output
40
Input signal, comes from microphone
41
I
Input signal, comes from magnetic head of tape
42
I
IC test pin, Active Low
58
49
48
47
I/O
I/O
I/O
I/O
P
Extra I/O port 1
Extra I/O port 2
Extra I/O port 3
Extra I/O port 4
Logic power
68
21, 43
22
28
G
P
Logic ground
Analog power
Analog ground
When ROSC is selected, OPT is connected to VDD and if X’TAL is selected, OPT
G
* OPT is the selection pin for ROSC or X’TAL.
is floating or connected to GND.
type change.
The PCB layout that looks like in the right figure is proper. This will make it easier for OSC
VDD
OPT
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
4
SEP. 21, 2001
Version: 1.1
SPT5507A
5. FUNCTIONAL DESCRIPTIONS
The SPT5507A is a CMOS; low cost, audio processor that can
operate with a supply rang from 4.0V to 5.5V.
ports and an analog processor.
The SPT5507A
has mainly an 8-bit CPU, 128B SRAM, 40KB ROM, several I/O
The address map of memory and
The analog
I/O ports please refer to the programming guide.
processor is described in detail in next section.
5.2. Linear Block Description
There are four major parts in the linear block including signal
switches, gain amplifier, DAC converter and low pass filter.
sample and hold circuits.
In
recording mode, signal switches select desired inputs and turn on
Gain amplifier amplifies the selected
signal, and provides flexible gain–adjustment by external resisters
and capacitors. A/D converter, which uses SAR algorithm based
on CPU converts the amplified signal to digital signal, than store
those digital data into ARAM.
In playing back mode, D/A
converter converts digital signals, which comes from ARAM to
analog signal. Following that DAC, low-pass filter with external
resistors and capacitors is used to smooth the DAC output
waveform.
5.1. Clock Source Selection
There are two options for clock sources.
or connected to VSS, the crystal oscillator is selected.
pin connects to VDD, the less accurate R-oscillator is selected.
between XI and AVDD.
The clock frequency of ROSC depends on the resistor connected
The recommended value is 30K Ohms
for 3.58MHz and 16K Ohms for 6 MHz respectively.
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When OPT pin is open
If the OPT
to user programming guides for the detail information.
Note:
Heretofore, the above are just hardware descriptions. Please refer
© Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
SEP. 21, 2001
Version: 1.1
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