PJSD05CFN2
BI-DIRECTIONAL TVS
This bi-directional TVS has been designed to protect sensitive equipment against ESD and to prevent
Latch-Up events in CMOS circuitry operating at 5Vdc and below.This offers an integrated solution to
protect a single data line where the board space is a premium.
SPECIFICATION FEA
TURES
• 200W Power Dissipation (8/20s Waveform)
• Low Leakage Current, Maximum of 1
A@5Vdc
• IEC 61000-4-2 ESD 15kV air, 8kV Contact Compliance
•
Lead free in comply with EU RoHS 2002/95/EC directives.
• Green molding compound as per IEC61249 Std. . (Halogen Free)
0.022(0.55)
0.017(0.45)
0.026(0.65)
0.022(0.55)
DFN 2L
0.042(1.05)
0.037(0.95)
Unit
：
inch(mm)
• Very low Clamping voltage
MECHANICAL DATA
• Terminals : Solderable per MIL-STD-750, Method 2026
• Case : DFN 2L, Plastic
• Weight:0.00004 ounces, 0.0011 grams
• Marking : BT
0.002(0.05)MAX.
0.013(0.32)
0.008(0.22)
0.014(0.36)
APPLICATIONS
• Video I/O ports protection
• Set Top Boxes
• Portable Instrumentation
PIN NO.1
IDENTIFICATION
MAXIMUM RATINGS
Rating
Peak Pulse Power (8/20
s
Waveform)
Maximum Peak Pulse Current (8/20
s
Waveform)
ESD Voltage (HBM)
Op e ra ti ng J unc ti o n a nd S to r a g e Te m p e r a ture R a ng e
Symbol
Value
200
18
>25
-55 to +150
Units
W
A
kV
O
P
PP
I
PPM
V
ESD
T
J
,T
S TG
0.022(0.55)
0.017(0.45)
C
ELECTRICAL CHARACTERISTICS (T
A
=25
o
C)
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20s)
Clamping Voltage (8/20s)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V
WRM
V
BR
I
R
V
C
V
C
C
J
C
J
I
BR
=1mA
V
R
=5V
I
PP
=5A
I
PP
=15A
0 Vdc Bias f=1MHz
5 Vdc Bias f=1MHz
Conditions
Min.
-
6
-
-
-
-
-
Typ.
-
-
-
-
-
-
-
Max.
5.0
-
1.0
11
14
70
60
Units
V
V
A
V
V
pF
pF
REV.0.5-AUG.11.2009
PAGE . 1
PJSD05CFN2
MOUNTING PAD LAYOUT
DFN 2L
Unit
：
inch(mm)
0.043
(1.10)
0.017
(0.42)
0.010
(0.26)
0.028
(0.70)
0.027
(0.68)
ORDER INFORMATION
• Packing information
T/R - 8K per 7" plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2012
The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.
REV.0.5-AUG.11.2009
PAGE . 3
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
