ESMT
Flash
FEATURES
Single supply voltage 2.3~3.3V
Standard, Dual SPI
(Preliminary)
F25S04PA
2.5V Only 4 Mbit Serial Flash Memory
with Dual Output
Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 86MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 86MHz/ 100MHz
(100MHz / 172MHz/ 200MHz equivalent Dual SPI)
Low power consumption
- Active current: 25 mA
- Standby current: 5
μ
A
- Deep Power Down current: 3
μ
A
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
Program
- Byte programming time: 7
μ
s (typical)
- Page programming time: 1.5 ms (typical)
Erase
- Chip erase time 3 sec (typical)
- Block erase time 0.75 sec (typical)
- Sector erase time 150 ms (typical)
Page Programming
- 256 byte per programmable page
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
End of program or erase detection
Write Protect (
WP
)
Hold Pin ( HOLD )
All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID
F25S04PA –50PG
F25S04PA –86PG
F25S04PA –100PG
F25S04PA –50PAG
F25S04PA –86PAG
F25S04PA –100PAG
F25S04PA –50DG
F25S04PA –86DG
F25S04PA –100DG
F25S04PA –50HG
F25S04PA –86HG
F25S04PA –100HG
Speed
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
Package
8-lead SOIC
8-lead SOIC
8-lead SOIC
8-lead SOIC
8-lead SOIC
8-lead SOIC
8-pin PDIP
8-pin PDIP
8-pin PDIP
8-contact WSON
8-contact WSON
8-contact WSON
150 mil
150 mil
150 mil
200 mil
200 mil
200 mil
300 mil
300 mil
300 mil
6x5 mm
6x5 mm
6x5 mm
COMMENTS
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date:
Sep.
2009
Revision:
0.3
1/34
ESMT
GENERAL DESCRIPTION
(Preliminary)
F25S04PA
The F25S04PA is a 4Megabit, 2.5V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 2,048 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The device features sector erase architecture. The memory array
is divided into 128 uniform sectors with 4K byte each; 8 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
PIN CONFIGURATIONS
8- Lead SOIC
CE
1
8
VDD
SO
2
3
7
6
HOLD
SCK
WP
VSS
4
5
SI
Elite Semiconductor Memory Technology Inc.
Publication Date:
Sep.
2009
Revision:
0.3
2/34
ESMT
8- Pin PDIP
(Preliminary)
F25S04PA
CE
1
8
VDD
SO
2
3
7
6
HOLD
SCK
WP
VSS
4
5
SI
8- Contact WSON
CE
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
Elite Semiconductor Memory Technology Inc.
Publication Date:
Sep.
2009
Revision:
0.3
3/34
ESMT
PIN DESCRIPTION
Symbol
SCK
SI
(Preliminary)
F25S04PA
Pin Name
Serial Clock
Serial Data Input
Functions
To provide the timing for serial input and
output operations
To transfer commands, addresses or data
serially into the device.
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect (
WP
) pin is used to
enable/disable BPL bit in the status
register.
To temporality stop serial communication
with SPI flash memory without resetting
the device.
To provide power.
SO
CE
WP
Serial Data Output
Chip Enable
Write Protect
HOLD
VDD
VSS
Hold
Power Supply
Ground
FUNCTIONAL BLOCK DIAGRAM
Address
Buffers
and
Latches
X-Decoder
Flash
Y-Decoder
Control Logic
I/O Butters
and
Data Latches
Serial Interface
CE
SCK
SI
SO
WP
HOLD
Elite Semiconductor Memory Technology Inc.
Publication Date:
Sep.
2009
Revision:
0.3
4/34
ESMT
SECTOR STRUCTURE
(Preliminary)
F25S04PA
Table 1: F25S04PA Sector Address Table
Block
Sector
127
7
:
112
111
6
:
96
95
5
:
80
79
4
:
64
63
3
:
48
47
2
:
32
31
1
:
16
15
0
:
0
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
07F000H – 07FFFFH
:
070000H – 070FFFH
06F000H – 06FFFFH
:
060000H – 060FFFH
05F000H – 05FFFFH
:
050000H – 050FFFH
04F000H – 04FFFFH
:
040000H – 040FFFH
03F000H – 03FFFFH
:
030000H – 030FFFH
02F000H – 02FFFFH
:
020000H – 020FFFH
01F000H – 01FFFFH
:
010000H – 010FFFH
00F000H – 00FFFFH
:
000000H – 000FFFH
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Block Address
A18
A17
A16
Elite Semiconductor Memory Technology Inc.
Publication Date:
Sep.
2009
Revision:
0.3
5/34
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