PJSR05TB4 SERIES
LOW CAPACITANCE TVS AND DIODE ARRA
Y
This diode array is configured to protect up to two data transmission lines acting as a line terminator,
minimizing overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage
events as electrostatic discharges. Additionaly the TVS Device offers overvoltage transient
protection between the operating voltage bus and ground plane. New package SOT-543 offers an ideal solution,
minimizing board space in portable consumer appliactions.
FEATURES
• Peak power dissipation of 350W 8x20μs
• Maximum capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground
• Maximum leakage current of 1.0μA@VRWM
• New SMT package SOT-543
• IEC61000-4-2 compliant 15kV Air, 8kV contact
•
0.052(1.30)
0.043(1.10)
0.067(1.70)
0.059(1.50)
SOT-543
0.011(0.27)
0.006(0.17)
Unit
：
inch(mm)
0.067(1.70)
0.059(1.50)
0.044(1.10)
0.035(0.90)
0.024(0.60)
0.019(0.50)
MECHANICAL DATA
• Case: SOT-543, Molded Plastic
• Terminals: Solderable per MIL-STD-750, Method 2026
• Polarity: See circuit schematic below
• Approx. Weight: 0.002 grams
0.007(0.17)
0.002(0.07)
APPLICATIONS
• USB 2.0 and Firewire Ports Protection
• LAN / WLAN Access Point terminals
• HDMI V1.3 Video Port Protection
• DVI Port
0.012(0.30)
0.004(0.10)
MAXIMUM RATINGS T
J
=25
o
C unless otherwise noted
PARAMETER
Peak Pulse Power (8/20μs Waveform)
S o ld e r i ng Te m p e ra tur e , t m a x=1 0 s
Op e r a ti ng J unc ti o n Te m p e r a tur e Ra ng e
Storage Temperature Range
SYMBOL
P
PPM
T
L
T
J
T
STG
VALUE
350
260
-55 to + 125
-55 to + 150
UNIT
W
o
C
C
O
o
C
VREF 4
3 I/O1
GND1
REV.0.1-JAN.5.2010
2 I/O2
PAGE . 1
PJSR05TB4 SERIES
ELECTRICAL CHARACTERISTICS(T
J
=25
o
C) unless otherwise noted
PJSR05TB4
Marking R5
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20μs)
Clamping Voltage (8/20μs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
J
C
J
I
BR
=1mA
V
R
=5V
I
PP
=1A
I
PP
=5A
0 Vdc Bias f=1MH
Z
Between I/O pins and GND
0 Vdc Bias f=1MHz
Between I/O pins
Condition
Min.
-
6.2
-
-
-
-
-
Typ.
-
-
-
-
-
0.9
0.5
Max.
5
-
1
9
12
1.2
0.6
Units
V
V
μA
V
V
pF
pF
PJSR12TB4
Marking R2
Parameter
Symbol
V
RWM
V
BR
I
R
V
C
V
C
C
J
C
J
I
BR
=1mA
V
R
=12V
I
PP
=1A
I
PP
=5A
0 Vdc Bias f=1MH
Z
Between I/O pins and GND
0 Vdc Bias f=1MHz
Between I/O pins
Condition
Min.
-
13.3
-
-
-
-
-
Typ.
-
-
-
-
-
0.9
0.5
Max.
12
-
1
18
22
1.2
0.6
Units
V
V
μA
V
V
pF
pF
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20μs)
Clamping Voltage (8/20μs)
Off State Junction Capacitance
Off State Junction Capacitance
APPLICATION EXAMPLE
USB2.0 Connector
Vbus+
D+
D-
USB
Controller
REV.0.1-JAN.5.2010
PAGE . 2
PJSR05TB4 SERIES
MOUNTING PAD LAYOUT
SOT-543
Unit
：
inch(mm)
0.013
(0.34)
0.053
(1.35)
0.039
(1.0)
ORDER INFORMATION
• Packing information
T/R - 4K per 7" plastic Reel
T/R - 10K per 13" plastic Reel
LEGAL STATEMENT
Copyright PanJit International, Inc 2012
The information presented in this document is believed to be accurate and reliable. The specifications and information herein
are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit
does not convey any license under its patent rights or rights of others.
REV.0.1-JAN.5.2010
0.017
(0.45)
PAGE . 3
FPGA/CPLD
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