NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
184pin Two Bank Unbuffered DDR SDRAM MODULE
Based on DDR333 16Mx8 SDRAM
Features
• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
• Performance :
PC2700
Speed Sort
DIMM
CAS
Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
f
DQ
DQ Burst Frequency
2.5
166
6
333
-6
2
133
7.5
266
MHz
ns
MHz
Unit
• DRAM D
LL
aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
• Intended for 166 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= 2.5Volt ± 0.2, V
DDQ
= 2.5Volt ± 0.2
• Single Pulsed
RAS
interface
• SDRAMs have 4 internal banks for concurrent operation
• Module has two physical banks
• Differential clock inputs
• Data is read or written on both clock edges
Description
NT256D64S8HA0G-6 is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a dual-bank high-speed memory array. The 32Mx64 module is a two-bank DIMM that uses sixteen 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 333MHz. The DIMM is intended for use
in applications operating from 133 MHz to 166 MHz clock speeds with data rates of 266 to 333 MHz. Clock enable CKE0 and / or CKE1
controls all devices on the DIMM.
Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number
NT256D64S8HA0G-6
133MHz (7.5ns @ CL= 2 )
Speed
166MHz (7ns @ CL = 2.5 )
PC2700
32Mx64
Gold
2.5V
Organization
Leads
Power
Preliminary,
11/2001
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Pin Description
CK0, CK1, CK2
CK0
,
CK1
,
CK2
CKE0, CKE1
Differential Clock Inputs
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
DQ0-DQ63
DQS0-DQS7,
DQS9-DQS16
VDD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bidirectional data strobes
Power (2.5V)
Supply voltage for DQs(2.5V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply(2.5V)
RAS
CAS
WE
S0
,
S1
A0-A9, A11
A10/AP
BA0, BA1
V
REF
V
DDID
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
V
SS
DQ4
DQ5
V
DDQ
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
CKE1
V
DDQ
NC
DQ20
NC
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
53
54
55
56
57
58
59
60
61
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Front
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
NC
A0
NC
V
SS
NC
BA1
KEY
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Back
V
SS
A6
DQ28
DQ29
V
DDQ
DQS12
A3
DQ30
V
SS
DQ31
NC
NC
V
DDQ
CK0
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
V
DDQ
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
V
DDQ
WE
DQ41
CAS
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
S0
S1
DQS14
V
SS
DQ46
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
CK2
CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
CK0
V
SS
NC
A10
NC
V
DDQ
NC
KEY
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
CK1
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
Preliminary,
11/2001
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Input/Output Functional Description
Symbol
CK0 , CK1, CK2
Type
(SSTL)
Polarity
Positive
Edge
Function
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
edge of their associated clocks.
on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
RAS
,
CAS
,
WE
define the
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
A0 - A9
A10/AP
A11
(SSTL)
-
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63,
DQS0 - DQS7
DQS9 - DQS16
V
DD
, V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
Supply
(SSTL)
(SSTL)
Supply
-
-
-
-
Active
High
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pullup.
Serial EEPROM positive power supply.
CK0
,
CK1
,
CK2
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to the
Edge
Active
High
CKE0, CKE1
(SSTL)
S0
,
S1
(SSTL)
Active
Low
Active
Low
RAS
,
CAS
,
WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
Supply
Supply
(SSTL)
Preliminary,
11/2001
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Functional Block Diagram
( 2 Bank, 16Mx8 DDR SDRAMs )
S1
S0
DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQS4
DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0-BA1
A0-A11
RAS
CAS
CKE0
CKE1
WE
Notes :
1.
2.
3.
4.
BA0 - BA1 : SDRAMs D0 -D15
A0 - A11 : SDRAMs D0 -D15
RAS : SDRAMs D0 -D15
CAS : SDRAMs D0 -D15
CKE0 : SDRAMs D0 -D7
WE : SDRAMs D8 -D15
WE : SDRAMs D0 -D15
VDDQ
VDD
VREF
VSS
VDDID
D0 - D15
D0 - D15
D0 - D15
D0 - D15
Strap: see Note 4
CK0
120 ohm
CK0
CK1
120 ohm
CK1
CK2
120 ohm
SDRAM x 6
SDRAM x 6
SDRAM x 4
Serial PD
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
CK2
DQ-to-I/O wring may be changed within a byte.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22 Ohms.
VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
Preliminary,
11/2001
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT256D64S8HA0G-6
256MB : 32M x 64
PC2700 Unbuffered DIMM
Absolute Maximum Ratings
Symbol
V
IN
, V
OUT
V
IN
V
DD
V
DDQ
T
A
T
STG
P
D
I
OUT
Parameter
Voltage on I/O pins relative to Vss
Voltage on Input relative to Vss
Voltage on V
DD
supply relative to Vss
Voltage on V
DDQ
supply relative to Vss
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Power Dissipation
Short Circuit Output Current
Rating
-0.5 to V
DDQ
+0.5
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
0 to+70
-55 to +150
16
50
Units
V
V
V
V
°C
°C
W
mA
Note:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter
Input Capacitance: CK0,
CK0
, CK1,
CK1
, CK2,
CK2
Input Capacitance: A0-A11, BA0, BA1,
WE
,
RAS
,
CAS
Input Capacitance: CKE0, CKE1,
S0
,
S1
Symbol
C
I1
C
I2
C
I3
Max.
24
60
30
Units
pF
pF
pF
Notes
1
1
1
C
IO1
14
pF
1,2
Input/Output Capacitance DQ0-63; DQS0-7, 9-16
1. V
DDQ
= V
DD
= 2.5V ± 0.2V, f = 100 MHz, T
A
= 25
°C,
V
OUT
(DC) = V
DDQ/2
, V
OUT
(Peak to Peak) = 0.2V.
2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at
the board level.
Preliminary,
11/2001
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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