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CY7C107B-15VIT

器件型号:CY7C107B-15VIT
器件类别:存储    存储   
厂商名称:Cypress(赛普拉斯)
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器件描述

Standard SRAM, 1MX1, 15ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28

参数
参数名称属性值
是否Rohs认证不符合
零件包装代码SOJ
包装说明SOJ,
针数28
Reach Compliance Codeunknown
ECCN代码3A991.B.2.B
最长访问时间15 ns
JESD-30 代码R-PDSO-J28
JESD-609代码e0
长度18.415 mm
内存密度1048576 bit
内存集成电路类型STANDARD SRAM
内存宽度1
湿度敏感等级1
功能数量1
端子数量28
字数1048576 words
字数代码1000000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织1MX1
封装主体材料PLASTIC/EPOXY
封装代码SOJ
封装形状RECTANGULAR
封装形式SMALL OUTLINE
并行/串行PARALLEL
峰值回流温度(摄氏度)220
认证状态Not Qualified
座面最大高度3.7592 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层TIN LEAD
端子形式J BEND
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度10.16 mm
Base Number Matches1

文档预览

07B
CY7C107B
CY7C1007B
1M x 1 Static RAM
Features
• High speed
— t
AA
= 12 ns
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(D
IN
) is written into the memory location specified on the ad-
dress pins (A
0
through A
19
).
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (D
OUT
)
pin.
The output pin (D
OUT
) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
Functional Description
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
Logic Block Diagram
D
IN
Pin Configuration
SOJ
Top View
A
10
A
11
A
12
A
13
A
14
A
15
NC
A
16
A
17
A
18
A
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
512x2048
ARRA
Y
D
OUT
D
OUT
WE
GND
V
CC
A
9
A
8
A
7
A
6
A
5
A
4
NC
A
3
A
2
A
1
A
0
D
IN
CE
107B-2
COLUMN
DECODER
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
POWER
DOWN
SENSE AMPS
CE
WE
107B-1
Selection Guide
7C107B-12
7C1007B-12
12
90
2
7C107B-15
7C1007B-15
15
80
2
7C107B-20
7C1007B-20
20
75
2
7C107B-25
7C1007B-25
25
70
2
7C107B-35
7C1007B-35
35
60
2
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
Cypress Semiconductor Corporation
Document #: 38-05030 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised September 7, 2001
CY7C107B
CY7C1007B
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage on V
CC
Relative to GND
[1]
.....−0.5V
to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................... −0.5V
to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................... −0.5V
to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
[2]
0°C to +70°C
−40°C
to +85°C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C107B-12
7C1007B-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current— TTL Inputs
Automatic CE
Power-Down
Current—
CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
>V
IH
or V
IN
< V
IL
,
f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
−0.3
−1
–5
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+5
−300
90
2.2
−0.3
−1
–5
Max.
7C107B-15
7C1007B-15
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+5
−300
80
2.2
−0.3
−1
–5
Max.
7C107B-20
7C1007B-20
Min.
2.4
0.4
V
CC
+
0.3
0.8
+1
+5
−300
75
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
20
20
20
mA
I
SB2
2
2
2
mA
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Document #: 38-05030 Rev. **
Page 2 of 9
CY7C107B
CY7C1007B
Electrical Characteristics
Over the Operating Range (continued)
7C107B-25
7C1007B-25
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH
Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current—TTL Inputs
Automatic CE
Power-Down
Current—CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
>V
IH
or V
IN
< V
IL
,
f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
−0.3
−1
−5
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
−300
70
2.2
−0.3
−1
−5
Max.
7C107B-35
7C1007B-35
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
−300
60
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB1
20
20
mA
I
SB2
2
2
mA
Capacitance
[4]
Parameter
C
IN
: Addresses
C
IN
: Controls
C
OUT
Output Capacitance
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
7
10
10
Unit
pF
pF
pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05030 Rev. **
Page 3 of 9
CY7C107B
CY7C1007B
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 480Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
R1 480Ω
3.0V
GND
10%
3 ns
ALL INPUT PULSES
90%
90%
10%
3 ns
107-4
107-3
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
167Ω
1.73V
Switching Characteristics
[5]
Over the Operating Range
7C107B-12
7C1007B-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address
Change
CE LOW to Data Valid
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write
End
Address Hold from Write
End
Address Set-Up to Write
Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
3
6
0
12
15
12
12
0
0
12
8
0
3
7
3
6
0
15
20
15
15
0
0
15
10
0
3
8
3
12
3
7
0
20
25
20
20
0
0
20
15
0
3
10
12
12
3
15
3
8
0
25
35
25
25
0
0
25
20
0
3
10
15
15
3
20
3
10
0
35
20
20
3
25
3
10
25
25
3
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C107B-15
7C1007B-15
Min.
Max.
7C107B-20
7C1007B-20
Min.
Max.
7C107B-25
7C1007B-25
Min.
Max.
7C107B-35
7C1007B-35
Min.
Max.
Unit
WRITE CYCLE
[8]
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZCE
and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05030 Rev. **
Page 4 of 9
CY7C107B
CY7C1007B
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
107-6
Read Cycle No. 2
[11, 12]
ADDRESS
t
RC
CE
t
ACE
t
LZCE
DATA OUT
HIGH IMPEDANCE
DATA VALID
t
PD
50%
50%
I
CC
I
SB
107-7
t
HZCE
HIGH
IMPEDANCE
V
CC
SUPPLY
CURRENT
t
PU
Write Cycle No. 1 (CE Controlled)
[13]
t
WC
ADDRESS
t
SA
CE
t
AW
WE
t
PWE
t
SD
DATA IN
DATA VALID
t
HD
t
HA
t
SCE
DATA OUT
HIGH IMPEDANCE
107-8
Notes:
9. No input may exceed V
CC
+ 0.5V.
10. Device is continuously selected, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05030 Rev. **
Page 5 of 9
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