M12L16161A
512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
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GENERAL DESCRIPTION
JEDEC standard 3.3V power supply
The M12L16161A is 16,777,216 bits synchro-
LVTTL compatible with multiplexed address
nous high data rate Dynamic RAM organized as
Dual banks operation
2 x 524,288 words by 16 bits, fabricated with
MRS cycle with address key programs
high performance CMOS technology. Synchro-
- CAS Latency (2 & 3 )
nous design allows precise cycle control with the
- Burst Length (1, 2, 4, 8 & full page)
use of system clock I/O transactions are possible
- Burst Type (Sequential & Interleave)
on every clock cycle. Range of operating fre-
All inputs are sampled at the positive going edge quencies, programmable burst length and pro-
grammable latencies allow the same device to be
of the system clock
Burst Read Single-bit Write operation
useful for a variety of high bandwidth, high
performance memory system applications.
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
ORDERING INFORMATION
Part NO.
M12L16161A-4.3T
M12L16161A-5T
M12L16161A-5.5T
M12L16161A-6T
M12L16161A-7T
M12L16161A-8T
MAX Freq.
233MHz
200MHz
183MHz
166MHz
143MHz
125MHz
Interface
Package
LVTTL
50
TSOP(II)
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
P.1
Publication Date : Jan. 2000
Revision : 1.3u
M12L16161A
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Bank Select
Data Input Register
LWE
LDQM
Row Buffer
Refresh Counter
Row Decoder
Output Buffer
512K x 16
512K x 16
Sense AMP
Address Register
LRAS
CLK
CKE
DQi
CLK
ADD
LCBR
Col. Buffer
LRAS
Column Decoder
Latency & Burst Length
Programming Register
LCKE
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CS
RAS
CAS
WE
L(U)DQM
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10/AP
BA
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
RAS
CAS
Column Address Strobe
WE
L(U)DQM
DQ
0 ~ 15
V
DD
/V
SS
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
Elite Semiconductor Memory Technology Inc.
P.2
Publication Date : Jan. 2000
Revision : 1.3u
M12L16161A
V
DDQ
/V
SSQ
N.C/RFU
Data Output Power/Ground
No Connection/
Reserved for Future Use
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN,
V
OUT
V
DD
,V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ + 150
1
50
Unit
V
V
°
C
W
MA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70
°
C
)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Note :
Symbol
V
DD
,V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
uA
uA
Note
1
2
I
OH
=-2mA
I
OL
= 2mA
3
4
1.V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2.V
IL
(min) = -1.5V AC for pulse width
≤
10ns acceptable.
3.Any input 0V
≤
V
IN
≤
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V
≤
V
OUT
≤
V
DD
.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
°
C
, f = 1MHz)
Pin
CLOCK
RAS , CAS , WE , CS , CKE, LDQM,
UDQM
ADDRESS
DQ0 ~DQ15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
P.3
Publication Date : Jan. 2000
Revision : 1.3u
M12L16161A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C
V
IH
(min)/V
IL
(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non power-
down mode
Symbol
I
CC1
I
CC2
P
I
CC2
PS
I
CC2
N
Test Condition
CAS
Version
Latency -4.3 -5 -5.5 -6 -7
-8
Unit Note
1
Burst Length = 1
t
RC
≥
t
RC
(min),
t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max),
t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max),
t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max),
t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max),
t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max),
t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max),
t
CC
=
∞
Input signals are stable
I
OL
= 0Ma, Page Burst
All Band Activated,
t
CCD
=
t
CCD
(min)
3
2
250 230 210 190 160 140 mA
2
2
30
2
10
10
40
10
mA
mA
mA
mA
mA
mA
I
CC2
NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
I
CC3
P
I
CC3
PS
I
CC3
N
I
CC3
NS
I
CC
4
270 250 230 210 180 160 mA
270 250 230 210 180 160
270 250 230 210 180 160 mA
1
mA
1
I
CC
5
I
CC
6
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
2
Note:
1.Measured with outputs open. Addresses are changed only one time during
t
CC
(min).
2.Refresh period is 32ms. Addresses are changed only one time during
t
CC
(min).
Elite Semiconductor Memory Technology Inc.
P.4
Publication Date : Jan. 2000
Revision : 1.3u
M12L16161A
AC OPERATING TEST CONDITIONS
(V
DD
=3.3V
±
0.3V,T
A
= 0 to 70
°
C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
Vtt =1.4V
1200
è
50
Output
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
Output
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
Unit
V
V
ns
V
è
Z0=50
è
30 pF
870
è
30 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Symbol
-4.3
8.6
12.9
12.9
34.4
47.3
-5
10
15
15
40
55
Version
-5.5 -6
11
12
16
16
40
100
60
1
1
1
1
1
1
60
63
68
16
18
42
-7
14
16
20
42
-8
16
20
20
48
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
ea
1
2
2
2
3
4
Note
1
1
1
1
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
CAS latency=3
CAS latency=2
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
4. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
P.5
Publication Date : Jan. 2000
Revision : 1.3u
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