ESMT
SDRAM
M12S16161A
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
2.5V power supply
LVCMOS compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
CAS Latency (1, 2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
Special Function Support.
-
PASR (Partial Array Self Refresh )
-
TCSR (Temperature compensated Self Refresh)
-
DS (Driver Strength)
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
GENERAL DESCRIPTION
The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO.
M12S16161A-10T
M12S16161A-15T
M12S16161A-10TG
M12S16161A-15TG
MAX
Freq.
100MHz
66MHz
100MHz
66MHz
Interface Package Comments
Non-Pb-free
50
Non-Pb-free
TSOP(II)
Pb-free
Pb-free
LVCMOS
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
1/28
ESMT
FUNCTIONAL BLOCK DIAGRAM
M12S16161A
I/O Control
Bank Select
Data Input Register
LWE
LDQM
Row Buffer
Refresh Counter
Row Decoder
Sense AMP
Output Buffer
512K x 16
512K x 16
Address Register
LRAS
CLK
DQi
CLK
ADD
LCBR
LRAS
Col. Buffer
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CKE
L(U)DQM
CS
RAS
CAS
WE
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
CKE
A0 ~ A10/AP
BA
RAS
CAS
WE
Name
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE
active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
L(U)DQM
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
2/28
ESMT
DQ0 ~ 15
VDD/VSS
VDDQ/VSSQ
N.C/RFU
Data Input / Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
M12S16161A
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ + 150
0.7
50
Unit
V
V
°
C
W
MA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0
°C
~ 70
°C
)
Parameter
Supply voltage
Symbol
V
DD
V
DDQ
Min
2.3
2.3
Typ
2.5
2.5
Max
2.7
2.7
Unit
V
V
Note
1.65
-
2.7
V
1
Input logic high voltage
V
IH
0.8 x V
DDQ
-
V
DDQ
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.3
V
2
Output logic high voltage
V
OH
V
DDQ
– 0.2
-
-
V
I
OH
=-0.1mA
Output logic low voltage
V
OL
-
-
0.2
V
I
OL
= 0.1mA
Input leakage current
I
IL
-10
-
10
uA
3
Output leakage current
I
OL
-10
-
10
uA
4
Note :
1. ESMT can support VDDQ 2.5V (in general case) and 1.8V (in specific case) for VDD 2.5V products. Please contact
to sales. Dept. when condisering the use fo VDDQ 1.8V (min 1.65V).
2.V
IH
(max) = 4.6V AC for pulse width
≤
3ns acceptable.
3.V
IL
(min) = -1.0V AC for pulse width
≤
3ns acceptable.
4.Any input 0V
≤
V
IN
≤
V
DDQ
, all other pins are not under test = 0V.
5.Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ
.
CAPACITANCE
(V
DD
= 2.5V, T
A
= 25
°C
, f = 1MHz)
Pin
CLOCK
RAS , CAS ,
WE
, CS , CKE, LDQM,
UDQM
ADDRESS
DQ0 ~DQ15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
3/28
ESMT
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0
°C
~ 70
°C
)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Symbol
Test Condition
CAS
Latency
M12S16161A
Version
-10
35
-
0.2
-
-15
25
Unit Note
mA
mA
mA
mA
1
I
CC1
I
CC2P
I
CC2PS
I
CC2N
Burst Length = 1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
=15ns
CKE
≤
V
IL
(max), CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0Ma, Page Burst
All Band Activated, tCCD = tCCD (min)
t
RC
≥
t
RC
(min)
TCSR range
2 Banks
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
I
CC4
I
CC5
-
-
-
15
-
35
35
45
100
95
90
85
10
25
25
70
120
110
100
90
mA
mA
mA
mA
mA
1
mA
2
°C
Self Refresh Current
I
CC6
CKE
≤
0.2V
1 Bank
1/2 Bank
1/4 Bank
uA
Deep Power Down
Current
I
CC7
CKE
≤
0.2V
uA
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is 32ms. Addresses are changed only one time during t
CC
(min).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
4/28
ESMT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V,T
A
= 0 °C ~ 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
VDDQ
M12S16161A
Value
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
Unit
V
V
ns
V
Vtt =0.5x VDDQ
500
50
Output
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
500
30 pF
Output
Z0=50
20 pF
(Fig.1) DC Output Load circuit
(Fig.2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Symbol
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
CDL
(min)
t
RDL
(min)
t
BDL
(min)
t
CCD
(min)
CAS latency=3
Number of valid output data
CAS latency=2
CAS latency=1
70
1
2
1
1
2
1
0
ea
4
Version
-10
20
30
20
50
100
90
-15
30
30
30
60
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
1
2
2
2
3
Note
1
1
1
1
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
5/28
stm32/stm8
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