NT5DS4M32EF
4Mx32 Double Data Rate SDRAM
128Mbit DDR SDRAM
1M x 32Bit x 4 Banks
Double Data Rate Synchronous RAM
With Bi-directional Data Strobe and DLL
(144-Ball FBGA)
Nanya Technology Corp.
NTC reserves the right to change products or specification with out notice.
REV 0.3 (Preliminary)
09/2003
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS4M32EF
4Mx32 Double Data Rate SDRAM
TABLE OF CONTENTS
Table of Contents
Memory Part Numbering
General Description & Device Features
Pin Configuration & Pin Description
Input/Output Functional Description
Functional Block Diagram
Simplified State Diagram
Functional Description
Power up Sequence
Mode Register Set(MRS)
Extended Mode Register Set
Burst Mode Operation
Burst Length & Sequence
Bank Activation Command
Burst Read Operation
Burst Write Operation
Burst Interruption
Read Interrupt by Read
Read Interrupt by Burst Stop & Write
Read Interrupt by Precharge
Write Interrupt by Write
Write Interrupt by Read & DM
Write Interrupt by Precharge & DM
Burst Stop Command
DM Function
Auto Precharge Operation
Read with Auto Precharge
Write with Auto Precharge
Precharge Command
Auto Refresh
Self Refresh
Power Down Mode
Absolute Maximum Ratings
Power & DC Operating Conditions
DC Characteristics
AC Input Operating Conditions
AC Operating Test Conditions
Capacitance
Decoupling Capacitance Guide Line
AC Characteristics(I)
AC Characteristics(II)
Simplified Truth Table
Functional Truth Table
Functional Truth Table for CKE
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 9
- 10
- 11
- 12
- 12
- 12
- 13
- 13
- 14
- 14
- 14
- 15
- 15
- 16
- 17
- 18
- 18
- 19
- 19
- 20
- 20
- 21
- 21
- 22
- 23
- 23
- 24
- 24
- 25
- 25
- 25
- 26
- 27
- 28
- 29
- 31
2
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Timing
Basic Timing(@BL=2, CL=3)
Multi Bank Interleaving Read(@BL=4,CL=3)
Multi Bank Interleaving Write(@BL=4,CL=3)
Auto Precharge after Read Burst(@BL=8)
Auto Precharge after Write Burst(@BL=4)
Normal Write Burst(@BL=4)
Write Interrupt by Precharge & DM(@BL=8)
Read Interrupt by Precharge(@BL=8)
Read Interrupt by Read(@BL=8,CL=3)
DM Function only for Write(@BL=8)
Power up Sequence & Auto Refresh(CBR)
Mode Register Set
I/V Characteristics for Input and Output Buffer
Reduced Output Driver Characteristics
Impedance Match Output Driver Characteristics
Package Dimension(FBGA)
- 32
- 32
- 33
- 34
- 35
- 36
- 37
- 38
- 39
- 41
- 42
- 43
- 44
- 45
- 45
- 47
- 48
Read Interrupt by Burst Stop & Write(@BL=8,CL=3) - 40
REV 0.3 (Preliminary)
09/2003
NT5DS4M32EF
4Mx32 Double Data Rate SDRAM
1M x32Bit x4Banks Double Data Rate Synchronous RAM with Bi -directional Data Strobe and DLL
GENERAL DESCRIPTION
For 1M x 32Bit x 4 Bank DDR SDRAM
The NT5DS4M32EF is 134,217,728 bits of double data rate synchronous dynamic RAM organized as 4 x 1,048,576 bits by 32 I/Os.
Synchronous features with Data Strobe allow extremely high performance up to 3.2GB/s/chip. I/O transactions are possible on both
edges of the clock. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be
useful for a variety of high performance memory system applicati ons.
FEATURES
• Data I/O transaction on both edges of Data strobe
• 4 DQS (1 DQS/Byte)
• DLL aligns DQ and DQS transaction with Clock
transaction
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA package
• Maximum clock frequency up to 400MHz
• Maximum data rate up to 800Mbps/pin
• VDD = 2.5V±5% , VDDQ = 2.5V±5%
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. CAS latency 2,3, 4 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Differential clock input(CK & /CK)
ORDERING INFORMATION
Part NO.
NT5DS4M32EF -25
NT5DS4M32EF -28
NT5DS4M32EF -33
NT5DS4M32EF -4
NT5DS4M32EF -5
Max Freq.
400MHz
350MHz
300MHz
250MHz
200MHz
Max Data Rate
800Mbps/pin
700Mbps/pin
600Mbps/pin
500Mbps/pin
400Mbps/pin
SSTL_2
144-Ball FBGA
Interface
Package
REV 0.3 (Preliminary)
09/2003
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS4M32EF
4Mx32 Double Data Rate SDRAM
PIN CONFIGURATION (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
DQS0
DQ4
DQ6
2
DM0
VDDQ
DQ5
3
VSSQ
NC
VSSQ
4
DQ3
VDDQ
VSSQ
5
DQ2
DQ1
VSSQ
6
DQ0
VDDQ
VDD
7
DQ31
VDDQ
VDD
8
DQ29
DQ30
VSSQ
9
DQ28
VDDQ
VSSQ
10
VSSQ
NC
VSSQ
11
DM3
VDDQ
DQ26
12
DQS3
DQ27
DQ25
DQ24
DQ7
DQ17
DQ19
VDDQ
DQ16
DQ18
VDD
VDDQ
VDDQ
VSS
VSSQ
VSSQ
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSSQ
VSSQ
VDD
VDDQ
VDDQ
VDDQ
DQ15
DQ13
DQ14
DQ12
DQS1
DQS2
DQ21
DQ22
DM2
DQ20
DQ23
NC
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDQ
VDDQ
DM1
DQ11
DQ9
DQ10
DQ8
NC
/CAS
/RAS
/CS
/WE
NC
NC
VDD
NC
BA0
VSS
BA1
A0
A10
A2
A1
VDD
A11
A3
VDD
A9
A4
RFU1
A5
A6
VSS
RFU2
A7
VDD
CK
A8/AP
NC
/CK
CKE
MCL
VREF
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. VSS Thermal balls are optional
PIN Description
CK, /CK
CKE
/CS
/RAS
/CAS
/WE
DQS
DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~ A
11
DQ
0 ~
DQ
31
V
DD
V
SS
V
DDQ
V
SSQ
MCL
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ’
s
Ground for DQ’
s
Must Connect Low
REV 0.3 (Preliminary)
09/2003
4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS4M32EF
4Mx32 Double Data Rate SDRAM
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
The differential system clock inputs.
Function
CK, /CK
#
Input
All of the input are sampled on the rising edge of the clock exc ept DQ’ and
s
DM’ that are sampled on both edges of the DQS.
s
CKE
Input
CKE high activates and CKE low deactivates the internal clock,in put buffers and output drivers. By
deactivating the clock, CKE low indicates the Power down mode or Self refresh mode.
/CS
Input
/CS enables(registered Low) and disables(registered High) the com mand decoder. When /CS is
registered High,new commands are ignored but previous operations are continued.
/RAS
Input
Latc hes row addresses on the positive going edge of the CK with /RAS low.
Enables row access & precharge.
Latc hes Column addresses on the positive going edge of the CK with /CAS
low. Enables column access.
Enables write operation and row precharge.
Latc hes data in starting from /CAS, /WE active.
/CAS
Input
/W E
Input
DQS
0
~DQS
3
Input,Output
Data inputs and outputs are synchronized with both edge of DQS.
DQS
0
for DQ
0
~DQ
7
, DQS
1
for DQ
8
~DQ
15
, DQS
2
for DQ
16
~DQ
23
, DQS
3
for DQ
24
~DQ
31
DM
0
~ DM
3
Input
Data-In mask. Data-In is masked by DM Latency=0 when DM is high in burst write. DM
0
for DQ
0
~ DQ
7
,
DM
1
for DQ
8
~ DQ
15
, DM
2
for DQ
16
~ DQ
23
, DM
3
for DQ
24
~ DQ
31
.
DQ
0
~ DQ
31
Input,Output
Data inputs and outputs are multiplexed on the same pins.
BA
0
, BA
1
Input
Select which bank is to be active.
Row,Column addresses are multiplexed on the same pin. Row address : RA
0
~ RA
11
,
Column address : CA
0
~ CA
7
. Column address CA
8
is used for auto precharge.
A
0
~ A
11
Input
V
DD
,V
SS
Power Supply
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provi de improved
noise immunity.
Reference voltage for inputs, used for SSTL interface.
V
DDQ
,V
SSQ
Power Supply
V
REF
Power Supply
No Connection/
NC/RFU
Reserved for future use
This pin is recommended to be left “No Connection” on the device
MCL
Must Connect Low
Must Connect Low
#
: The timing reference point for the differential clocking is the cross point of CK and /CK.
For any applications using the single ended clocking, app ly V
REF
to /CK pin.
REV 0.3 (Preliminary)
09/2003
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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