NT5DS64M8DS
NT5DS32M16DS
512Mb DDR SDRAM
Feature
CAS Latency Frequency
DDR-333
DDR400
-5T/-5TI
DDR500
2KB
page size for all configurations.
Units
Speed Sorts
-6K/-6KI
CL-tRCD-tRP
-4T
DQS is edge-aligned with data for reads and is
center-aligned with data for WRITEs
2.5-3-3
266
333
333
3-3-3
266
333
400
3-4-4
-
333
500
tCK
CL=2
Speed
CL=2.5
CL=3
Differential clock inputs (CK and
)
Mbps
Data mask (DM) for write data
DLL aligns DQ and DQS transition with CK transitions.
Commands entered on each positive CK edge; data
Power Supply Voltage:
V
DD
=V
DDQ
=2.5V±0.2V (DDR-333)
V
DD
=V
DDQ
=2.6V±0.1V (DDR-400/500)
and data mask referenced to both edges of DQS
Burst Lengths: 2, 4 or 8
Auto Precharge option for each burst access
Auto-Refresh and Self-Refresh Mode
7.8 µs max. Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
RoHS and Halogen-Free compliance
Packages: 66 pin TSOPII
4 internal memory banks for concurrent operation.
CAS Latency: 2, 2.5 and 3
Double Data Rate Architecture
Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver.
Industrial grade device support -40℃~85℃ Operating
Temperature (-75I/-6KI/5TI)
Commercial grade device support 0℃~70℃ Operating
Temperature (-75/-6K/5T)
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REV 1.1
Sept. 2013
CONSUMER DRAM
NT5DS64M8DS
NT5DS32M16DS
512Mb DDR SDRAM
Description
Nanya 512Mb SDRAMs is a high-speed CMOS Double Data Rate SDRAM containing 536,870,912 bits. It is internally
configured as a qual-bank DRAM.
The 512Mb chip is organized as 16Mbit x 8 I/O x 4 bank or 8Mbit x 16 I/O x 4 bank device. These synchronous devices
achieve high speed double-data-rate transfer rates of up to 500 (400, 333 or 266) MHz for general applications.
The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high speed operation. The double data rate
architecture is essentially a 2η prefetch architecture with an interface designed to transfer two data words per clock cycle at
the I/O pins. A single read or write access for the 512Mb DDR SDRAM effectively consists of a single
2n-bit
wide, one clock
cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the
I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with
data for Reads and center-aligned with data for Writes.
The 512Mb DDR SDRAM operates from a differential clock (CK and
;
the crossing of CK going high and
going LOW
is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of
CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command,
which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or
Write command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.
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REV 1.1
Sept. 2013
CONSUMER DRAM
NT5DS64M8DS
NT5DS32M16DS
512Mb DDR SDRAM
Ordering Information
Standard Grade
Organization
64M x 8
32M x 16
Part Number
NT5DS64M8DS – 6K
NT5DS64M8DS – 5T
NT5DS32M16DS – 6K
NT5DS32M16DS – 5T
Package
66 pin
TSOP-II
Industrial Grade
Organization
64M x 8
32M x 16
Part Number
NT5DS64M8DS – 6KI
NT5DS64M8DS – 5TI
NT5DS32M16DS – 6KI
NT5DS32M16DS – 5TI
Package
66 pin
TSOP-II
Speed
Clock (MHz)
CL-T
RCD
-T
RP
166
2.5-3-3
200
3-3-3
166
2.5-3-3
200
3-3-3
Speed
Clock (MHz)
CL-T
RCD
-T
RP
166
2.5-3-3
200
3-3-3
166
2.5-3-3
200
3-3-3
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REV 1.1
Sept. 2013
CONSUMER DRAM
NT5DS64M8DS
NT5DS32M16DS
512Mb DDR SDRAM
Pin Configuration
– 400 mil TSOP II
(x4 / x8 / x16)
< TOP View>
See the balls through the package
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM*
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66-pin Plastic TSOP-II
400mil
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM*
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM*
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
32Mb x 16
64Mb x 8
Organization
64Mb x 8
32Mb x 16
Column Address
A0-A9, A11
A0-A9
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REV 1.1
Sept. 2013
CONSUMER DRAM
NT5DS64M8DS
NT5DS32M16DS
512Mb DDR SDRAM
Input / Output Functional Description
Symbol
CK,
Type
Input
Function
Clock:
CK and
are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of
.
Output (read) data is referenced to the crossings of CK and
(both directions of crossing).
Clock Enable:
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and
output drivers. Taking CKE LOW provides PRECHARGE POWER--DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER--DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-- DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output
disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK
and CKE are disabled during POWER--DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied upon 1st power up. After VREF
has become stable during the power on and initialization sequence, it must be maintained for proper operation of
the CKE receiver. For proper self--refresh entry and exit, VREF must be maintained to this input The standard
pinout includes one CKE pin. Optional pinouts include CKE0 and CKE1 on different pins, to facilitate device
stacking.
Chip Select:
All commands are masked when
is registered high.
provides for external rank selection on
systems with multiple memory ranks.
is considered part of the command code.
Command Inputs:
,
and
(along with
)
define the command being entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along
with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading. For the X16, LDM corresponds to the data on DQ0--DQ7;
UDM corresponds to the data on DQ8--DQ15. DM may be driven high, low, or floating during READs.
Bank Address Inputs:
BA# defines to which bank an Active, Read, Write or Pre-charge command is being
applied.
Address Inputs:
Provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective
bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op--code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
Data Bus:
Inputs/Output
Data Strobe:
Output
Input/output
CKE
Input
, ,
DM, LDM, UDM
Input
Input
Input
BA0 – BA1
Input
A0 – A12
Input
DQ
DQS, ()
LDQS, (),
UDQS,()
Input/output
with read data, input with write data. Edge--aligned with read data,
centered in write data. Used to capture write data. For the X16, LDQS corresponds to the
data on DQ0--DQ7; UDQS corresponds to the data on DQ8--DQ15.
Read Data Strobe:
For x8 components a RDQS and
pair can be enabled via EMRS(1) for real timing.
RDQS and
is not support x16 components. RDQS and
are edge-aligned with real data. If enable
RDQS and
then DM function will be disabled.
No Connect:
No internal electrical connection is present.
RDQS, ()
NC
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Input/output
Supply
Supply
Supply
Supply
Supply
DQ Power Supply:
DQ Ground
Power Supply:
Ground
2.5V ± 0.2V (-6K/-6KI); VDD=VDDQ=2.6V±0.1V (-5T/-5TI/-4T)
2.5V ± 0.2V (-6K/-6KI); VDD=VDDQ=2.6V±0.1V (-5T/-5TI/-4T)
SSTL_2 reference voltage
5
REV 1.1
Sept. 2013
CONSUMER DRAM
嵌入式系统
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