UTRON
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62256C is a 262,144-bit low power
CMOS static random access memory
organized as 32,768 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
The UT62256C is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
The UT62256C operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible
UT62256C
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 3mA (typical) normal
2uA (typical) L-version
1uA (typical) LL-version
Single 5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
A4
A3
A14
A13
A12
A7
A6
A5
A8
ROW
DECODER
PIN CONFIGURATION
A14
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
WE
.
.
.
MEMORY ARRAY
512 ROW × 512 COLUMNS
S
A7
A13
A8
A9
A11
OE
VCC
VSS
A6
A5
A4
A3
A2
A1
A0
I/O1
UT62256C
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
.
I/O1
.
.
I/O8
. .
COLUMN I/O
I/O2
I/O3
Vss
.
.
.
.
I/O
CONTROL
.
.
.
COLUMN DECODER
LOGIC
CONTROL
PDIP/SOP
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
A10
CE
WE
OE
A10 A9 A11 A2 A1 A0
A11
A9
A8
A13
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
V
CC
V
SS
WE
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
Vcc
A14
A12
A7
A6
A5
A4
A3
UT62256C
22
21
20
19
18
17
16
15
STSOP
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
1
UTRON
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UT62256C
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec0
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to +7.0
0 to +70
-65 to +150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for
extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
H = V
IH
, L=V
IL
, X = Don't care.
CE
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
I/O OPERATION
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
ISB, ISB1
I
CC
I
CC
I
CC
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10%, TA = 0
℃
to 70
℃
)
PARAMETER
SYMBOL
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input Leakage Current
I
LI
Output Leakage
I
LO
Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
V
OH
V
OL
I
CC
I
CC
1
I
CC
2
Standby Power
Supply Current
I
SB
I
SB1
I
SB
I
SB1
TEST CONDITION
MIN. TYP. MAX. UNIT
2.2
-
VCC+0.5 V
- 0.5
-
0.8
V
-1
-
1
µA
-1
-
1
µA
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC
CE =V
IH
or OE = V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
- 35
CE = V
IL
,
I
I/O
= 0mA ,Cycle=Min. - 70
CE = 0.2V; I
I/O
= 0mA Tcycle
other pins at 0.2V or =500ns
Tcycle
V
CC
-0.2V
=1ms
normal
CE =V
IH
CE
≧
V
CC
-0.2V
CE =V
IH
CE
≧
V
CC
-0.2V
-L/-LL
-L
-LL
2.4
-
-
-
-
-
-
-
-
-
-
-
40
30
-
-
1
0.3
-
2
1
-
0.4
50
40
20
10
10
5
3
100
50
V
V
mA
mA
mA
mA
mA
mA
mA
µA
µA
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
2
UTRON
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UT62256C
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10% , TA = 0
℃
to 70
℃
)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62256C-35
MIN.
MAX.
UT62256C-70
MIN.
MAX.
UNIT
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
SYMBOL
35
-
-
-
10
5
-
-
5
-
35
35
25
-
-
25
25
-
70
-
-
-
10
5
-
-
5
-
70
70
35
-
-
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
UT62256C-35
MIN.
MAX.
UT62256C-70
MIN.
MAX.
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
35
30
30
0
25
0
20
0
5
-
-
-
-
-
-
-
-
-
-
15
70
60
60
0
50
0
30
0
5
-
-
-
-
-
-
-
-
-
-
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
3
UTRON
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UT62256C
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
t
AA
t
OH
t
OH
DOUT
Data Valid
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,5,6)
t
RC
Address
t
AA
CE
t
ACE
OE
t
OE
t
CLZ
D
OUT
t
OLZ
High-z
t
CHZ
t
OHZ
t
OH
Data valid
High-Z
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected CE =V
IL.
3. Address must be valid prior to or coincident with CE transition; otherwise t
AA
is the limiting parameter.
4. OE is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
= 5pF. Transition is measured
±500mV
from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
Rev. 1.0
32K X 8 BIT LOW POWER CMOS SRAM
UT62256C
WRITE CYCLE 1
(
WE
Controlled)
(1,2,3,5)
t
WC
Address
t
AW
CE
t
AS
WE
t
CW
t
WP
t
WR
t
WHZ
D
OUT
High-Z
t
OW
(4)
(4)
t
DW
t
DH
Data Valid
D
IN
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5)
t
WC
Address
t
AW
CE
t
AS
t
CW
t
WP
t
WR
WE
t
WHZ
D
OUT
High-Z
(4)
t
DW
t
DH
D
IN
Data Valid
Notes :
1.
WE
or CE must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE and a low
WE
.
3. During a
WE
controlled with write cycle with OE LOW, t
WP
must be greater than t
WHZ
+t
DW
to allow the drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CE LOW
transition occurs simultaneously with or after
WE
outputs remain in a high impedance state.
6. t
OW
and
t
WHZ
are specified with C
L
= 5pF.
LOW
transition, the
Transition is measured
±500mV
from steady state.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
