UTRON
Rev. 1.0
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Rev. 1.0
DESCRIPTION
Original.
DATE
Sep 3 ,2001
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80071
1
UTRON
Rev. 1.0
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62256C(E) is a 262,144-bit low power CMOS
static random access memory organized as 32,768
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT62256C(E) is designed for high-speed and
low power application. It is particularly well suited
for battery back-up nonvolatile memory application.
The UT62256C(E) operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible
FEATURES
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 2uA (typ.) L-version
1uA (typ.) LL-version
Single 5V power supply
Extended temperature : -20
℃
~80
℃
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
PIN CONFIGURATION
A14
A12
1
2
3
4
28
27
26
25
Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
32K
×
8
MEMORY
ARRAY
A7
A6
A5
A4
A13
A8
A9
A11
OE
A0-A14
DECODER
UT62256C
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
Vcc
Vss
A3
A2
A1
A10
CE
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
A0
I/O1
I/O2
I/O3
Vss
I/O8
I/O7
I/O6
I/O5
I/O4
CE
WE
PDIP/SOP
CONTROL
CIRCUIT
OE
A11
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
A10
OE
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
V
CC
V
SS
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
UT62256C
21
20
19
18
17
16
15
STSOP
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80071
2
UTRON
Rev. 1.0
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
SYMBOL
V
TERM
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to +7.0
0 to +70
-65 to +150
1
50
260
UNIT
V
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
H = V
IH
, L=V
IL
, X = Don't care.
CE
H
L
L
L
OE
X
H
L
X
WE
X
H
H
L
I/O OPERATION
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
I
SB
, I
SB
1
I
CC,
I
CC
1, I
CC
2
I
CC,
I
CC
1, I
CC
2
I
CC,
I
CC
1, I
CC
2
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V±10%, T
A
= -20
℃
~80
℃
)
PARAMETER
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
SYMBOL
TEST CONDITION
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
I
CC
I
CC
1
I
CC
2
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC
CE =V
IH
or OE = V
IH
or
WE
= V
IL
I
OH
= - 1mA
I
OL
= 4mA
Cycle time=Min
- 35
- 70
CE = V
IL
,I
I/O
= 0mA ,.
Cycle time=1µs, CE =0.2V; I
I/O
=0mA,
other pins at 0.2V or V
CC
-0.2V
Cycle time=500ns, CE =0.2V;I
I/O
=0mA,
other pins at 0.2V or V
CC
-0.2V
CE =V
IH
-L
-
CE
≧
V
CC
-0.2V
-LL
MIN.
2.2
- 0.5
-1
-1
2.4
-
-
-
-
-
-
-
TYP. MAX.
-
V
CC
+0.5
-
0.8
-
1
-
1
-
-
40
30
-
-
-
2
1
-
0.4
50
40
10
20
3
100
50
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
µA
µA
Standby Current
(TTL)
Standby Current
(CMOS
)
I
SB
I
SB1
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80071
3
UTRON
Rev. 1.0
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(TA=25
℃
, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V±10% , T
A
= -20
℃
~80
℃
)
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
SYMBOL
UT62256C(E)-35
MIN.
MAX.
UT62256C(E)-70
MIN.
MAX.
UNIT
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
35
-
-
-
10
5
-
-
5
-
35
35
25
-
-
25
25
-
70
-
-
-
10
5
-
-
5
-
70
70
35
-
-
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
UT62256C(E)-35
MIN.
MAX.
UT62256C(E)-70
MIN.
MAX.
UNIT
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
35
30
30
0
25
0
20
0
5
-
-
-
-
-
-
-
-
-
-
15
70
60
60
0
50
0
30
0
5
-
-
-
-
-
-
-
-
-
-
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80071
4
UTRON
Rev. 1.0
UT62256C(E)
32K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2)
t
RC
Address
t
AA
t
OH
Dout
Previous data valid
Data Valid
t
OH
READ CYCLE 2
(
CE
and
OE
Controlled)
(1,3,4,5)
t
RC
Address
t
AA
CE
t
ACE
OE
t
OE
t
CLZ
t
OLZ
Dout
High-Z
Data Valid
t
CHZ
t
OHZ
t
OH
High-Z
Notes :
1.
WE
is high for read cycle.
2.Device is continuously selected OE =low, CE =low
.
3.Address must be valid prior to or coincident with CE =low
,
; otherwise t
AA
is the limiting parameter.
4.t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with C
L
=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
is less than t
OHZ
is less than t
OLZ
.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80071
5
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