UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
Preliminary Rev. 0.1
Rev. 1.0
Rev. 1.1
DESCRIPTION
Original.
Revised
-
The timeing waveforms add CE2 control pin
Revised
-
Package outline dimension
-
Waveform.
Revised
-
Improve I
DR
from 20µA to 10µA (LL-version , max.)
-
28-pin PDIP package outline dimension
1. Add Extended temperature : -20
℃
~85
℃
2. Revised Operating : 45/30 mA (typ.) 40/30 mA (typ.)
3. Revised CMOS Standby : 2 0.3mA (typ.) normal
4. Revised DC characteristics :
a. Icc(-35) : 45 40mA (typ.), 60 50 mA (max)
b. Icc(-70) : 45 40mA (max.)
c. Icc1(Tcycle=1us)= 10mA(max.)
d. Icc2(Tcycle=500ns)=20mA(max.)
5. Revised “Order information” : add Extended parts
Add order information for lead free product
Date
May 3 ,2001
Jun.4,2001
Jan 15,2002
Rev. 1.2
May 14,2002
Rev. 1.3
Jul 30,2002
Rev. 1.4
May 15,2003
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
1
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT6264C is a 65,536-bit low power CMOS static
random access memory organized as 8,192 words by
8 bits. It is fabricated using high performance, high
reliability CMOS technology.
Easy memory expansion is provided by using two
chip enable input.( CE ,CE2) ,and supports low data
retention voltage for battery back-up operation with
low data retention current.
The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully TTL
compatible.
FEATURES
Access time : 35/70ns (max.)
Low power consumption :
Operating : 40/30 mA (typ.)
CMOS Standby : 0.3mA (typ.) normal
2
µA
(typ.) L-version
1
µA
(typ.) LL-version
Single 4.5V~5.5V power supply
Operating temperature :
Commercial : 0℃~70℃
Extended : -20℃~85℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
PIN CONFIGURATION
NC
A12
A7
1
2
3
4
28
27
26
25
Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
A0-A12
DECODER
8K X 8
MEMORY
ARRAY
CE2
A8
A9
A11
OE
A6
A5
A4
A3
A2
A1
A0
UT6264C
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
Vcc
Vss
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
I/O1
I/O2
I/O3
Vss
PDIP/SOP
CE
CE2
OE
PIN DESCRIPTION
CONTROL
CIRCUIT
WE
SYMBOL
A0 - A12
I/O1 - I/O8
CE ,CE2
WE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No connection
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
2
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
SYMBOL
V
TERM
T
A
T
A
T
STG
P
D
I
OUT
Tsolder
RATING
-0.5 to 7.0
0 to 70
-20 to 85
-65 to 150
1
50
260
UNIT
V
℃
℃
℃
W
mA
℃
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Terminal Voltage with Respect to V
SS
Operating Temperature
Commercial
Extended
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 sec)
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Standby
Output Disable
Read
Write
CE
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
WE
X
X
H
H
L
I/O OPERATION
High - Z
High - Z
High - Z
D
OUT
D
IN
SUPPLY CURRENT
ISB, ISB1
ISB, ISB1
Icc,Icc1,Icc2
Icc,Icc1,Icc2
Icc,Icc1,Icc2
note: H = V
IH
, L=V
IL
, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V~5.5V, T
A
= 0℃ to 70℃/-20℃ to 85℃(E))
SYMBOL TEST CONDITION
MIN. TYP. MAX.
＊
1
V
IH
2.2
-
V
CC
+0.5
＊
2
V
IL
- 0.5
-
0.8
-1
-
1
I
LI
V
SS
≦
V
IN
≦
V
CC
V
SS
≦
V
I/O
≦
V
CC;
CE =V
IH;
or CE2=V
IL;
Output Leakage Current
I
LO
-1
-
1
or
OE
= V
IH
;
or WE = V
IL
Output High Voltage
V
OH
I
OH
= -1mA
2.4
-
-
Output Low Voltage
V
OL
I
OL
= 4mA
-
-
0.4
- 35
-
40
50
CE = V
IL
,
I
CC
- 70
-
30
40
I
I/O
= 0mA ,Cycle=Min.
Operating Power
Tcycle
-
-
10
CE = 0.2V; I
I/O
= 0mA;
Icc1
Supply Current
=1µs
CE2=Vcc-0.2V;
-
20
other pins at 0.2V or V
CC
-0.2V Tcycle -
Icc2
=500ns
normal
I
SB
-
1
10
CE =V
IH
or CE2= V
IL
Standby Power
Supply Current
I
SB1
I
SB
I
SB1
CE
≧
V
CC
-0.2V
or CE2
≦
0.2V
CE =V
IH
or CE2= V
IL
CE
≧V
CC
-0.2V
or CE2
≦
0.2V
0.3
-L/-LL
-L
-LL
-
-
-
-
2
1
5
3
100
50
PARAMETER
Input High Voltage
Input Low Voltage
Input Leakage Current
UNIT
V
V
µA
µA
V
V
mA
mA
mA
mA
mA
mA
mA
µA
µA
Notes:
1. Overshoot : Vcc+2.0v for pulse width less than 10ns.
2. Undershoot : Vss-2.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
3
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE
(T
A
=25℃, f=1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
8
10
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 3.0V
5ns
1.5V
C
L
= 100pF, I
OH
/I
OL
= -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 4.5V~5.5V, T
A
= 0
℃
to 70
℃/
-20
℃
to 85
℃
(E))
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z
SYMBOL
UT6264C-35
MIN.
MAX.
SYMBOL
UT6264C-35
MIN.
MAX.
UT6264C-70
MIN.
MAX.
UNIT
t
RC
t
AA
t
ACE
t
OE
t
CLZ*
t
OLZ*
t
CHZ*
t
OHZ*
t
OH
35
-
-
-
10
5
-
-
5
-
35
35
25
-
-
25
25
-
70
-
-
-
10
5
-
-
5
-
70
70
35
-
-
35
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
UT6264C-70
MIN.
MAX.
UNIT
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW*
t
WHZ*
35
30
30
0
25
0
20
0
5
-
-
-
-
-
-
-
-
-
-
15
70
60
60
0
50
0
30
0
5
-
-
-
-
-
-
-
-
-
-
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
4
NXP MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
